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[None][perf] Enable tiled FP8 context FMHA for head_dim 256 on SM120 - #19825

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amukkara merged 1 commit into
NVIDIA:mainfrom
amukkara:fmha-sm120-tile
Oct 8, 2026
Merged

amukkara merged 1 commit into
NVIDIA:mainfrom
amukkara:fmha-sm120-tile

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@amukkara amukkara commented Oct 2, 2026 •

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Description

Use tiled fmha_v2 kernel for FP8 (E4M3) context attention with head_dim 256 on SM120/SM121. Targets nvidia/Qwen3.6-35B-A3B-NVFP4 which uses FP8 KV cache.

  • cpp/kernels/fmha_v2/setup.py: add a tiled 64x128 QMMA kernel for head_dim 256, alongside the existing non-tiled 64x32 kernel.
  • fmhaRunner.cpp: restrict the forced non-tiled FP8 selection to SM89, so SM120/SM121 use the existing head-size heuristic, which selects tiled kernels for head_dim >= 256.

Performance

fmha_v2 harness on RTX PRO 6K BSE, FP8 Q/K/V, head_dim 256, tiled vs non-tiled kernel.
The tiled kernel is faster on all 35 shapes tested: 2.03x - 3.52x, geomean 3.01x.

sweep range speedup
KV length (b=1, 16 Q / 4 KV heads) 65 -> 32k 2.15x -> 3.32x
batch size 4 -> 64 at KV 256 / 1k / 4k 2.03x -> 3.24x
head config 8/2, 32/8, 32/32 2.93x -> 3.23x
chunked prefill query chunk 128 / 512, KV 2k / 8k 3.38x -> 3.43x
packed QKV, padding mask, FP8 output KV 1k / 4k 2.99x -> 3.52x

Test Coverage

The tiled kernel passes the fmha_v2 harness reference check on SM120 (-epsilon 0.2) for paged KV and packed QKV; causal, padding, sliding-window and custom masks; ALiBi; GQA; chunked prefill; and FP8 and BF16 output.

e2e accuracy verified by tests/integration/defs/accuracy/test_llm_api_pytorch.py::TestQwen3_6_35B_A3B::test_nvfp4_w4a16

Dev Engineer Review

setup.py adds an SM120-only tiled 64x128 QMMA configuration for FP8 E4M3 with head_dim 256. fmhaRunner.cpp limits forced non-tiled FP8 selection to SM89, allowing SM120/SM121 to use the existing tiling heuristic. The reported benchmark and accuracy results are author-reported; no test execution results were provided.

QA Engineer Review

No test changes.

Per-File QA Perspective

  • cpp/kernels/fmha_v2/setup.py: Adds a tiled-kernel configuration for SM120 and head_dim 256. QA should verify kernel selection and output correctness for supported shapes.
  • cpp/tensorrt_llm/kernels/contextFusedMultiHeadAttention/fmhaRunner.cpp: Changes FP8 E4M3 kernel selection for SM120/SM121. QA should verify that the tiling heuristic selects the expected kernel and preserves output correctness.

PR Checklist

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@amukkara
amukkara marked this pull request as ready for review October 2, 2026 23:58
@amukkara
amukkara requested a review from a team as a code owner October 2, 2026 23:58
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Review in Change Stack →

No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info
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📥 Commits

Reviewing files that changed from the base of the PR and between 54f2dbc and 886388c.

📒 Files selected for processing (1)
  • cpp/tensorrt_llm/kernels/contextFusedMultiHeadAttention/fmhaRunner.cpp

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Walkthrough

The FMHA kernel enumerator adds an SM120 tiled configuration for head size 256. The runner routes SM120/SM121 E4M3 cases through tiled-kernel selection. The setup file updates its copyright range through 2026.

Changes

SM120 FMHA kernel selection

Layer / File(s) Summary
Tiled kernel configuration and selection
cpp/kernels/fmha_v2/setup.py, cpp/tensorrt_llm/kernels/contextFusedMultiHeadAttention/fmhaRunner.cpp
The enumerator adds an SM120 tiled configuration for head size 256 with Q/KV loop steps 64/128. The runner limits the E4M3 non-tiled-kernel branch to SM89.

Priority: ➖ Normal

Estimated code review effort: 2 (Simple) | ~10 minutes

Change: Feature

Suggested reviewers: brnguyen2

Merge Risk: ⚪ Minimal · up to 88638

No specific user-impacting issue was established in the changed kernel-selection path; unsupported configurations retain the unfused fallback.

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 66.67% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 3 functions across 2 files. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (4 passed)
Check name Status Explanation
Title check ✅ Passed The title clearly summarizes the main change: enabling tiled FP8 context FMHA for head_dim 256 on SM120. It uses the repository’s ticket and type format.
Description check ✅ Passed The description explains the change and its purpose, reports performance results, identifies test coverage, and completes the PR checklist. It provides the key information required by the template.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
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Signed-off-by: Anurag Mukkara <134339030+amukkara@users.noreply.github.com>
@amukkara

amukkara commented Oct 6, 2026

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/bot run --disable-fail-fast

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PR_Github #76442 [ run ] triggered by Bot. Commit: 886388c Link to invocation

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PR_Github #76442 [ run ] completed with state FAILURE. Commit: 886388c
/LLM/main/L0_MergeRequest_PR pipeline #63032 completed with status: 'FAILURE'

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/bot run --disable-fail-fast

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PR_Github #76489 [ run ] triggered by Bot. Commit: 886388c Link to invocation

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PR_Github #76489 [ run ] completed with state SUCCESS. Commit: 886388c
/LLM/main/L0_MergeRequest_PR pipeline #63069 completed with status: 'SUCCESS'

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pengbowang-nv requested a review from bobboli October 8, 2026 06:41

@farazkh80 farazkh80 left a comment

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LGTM, thanks!

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Automatically added "ci: full pre-merge approved" because this PR has satisfied the required GitHub review approvals. Unresolved review conversations and other required checks remain independent merge requirements.

@amukkara
amukkara merged commit ac3ec50 into NVIDIA:main Oct 8, 2026
vsabavat added a commit to vsabavat/TensorRT-LLM that referenced this pull request Oct 9, 2026
Main's NVIDIA#19896 (2681ed1) moved PyTorchModelEngine's decoder execution
into DecoderRunner (engine/runners/decoder/runner.py) and the
encoder-decoder fast path into EncoderDecoderRunner, so this branch's
model_engine.py changes conflicted. model_engine.py is main's; the
branch's changes move to where that code now lives:
- DecoderRunner, from NVIDIA#19816 (U1): the step-copy gather, the staged
  previous batch / position indices, gather_ids written by
  copy_to_device_if_changed, no num_accepted_draft_tokens buffer, and
  the CUDA graphs' static inputs; from NVIDIA#19814 (U3): the gather of
  vocabulary-sharded logits for post-processors.
- EncoderDecoderRunner: its previous_batch_indices_cuda write clears the
  staged batch indices.
- The two tests that called the moved members call the runner.
Main's other commits since f891b3d: NVIDIA#19484, NVIDIA#19892, NVIDIA#19409, NVIDIA#19553,
NVIDIA#19957, NVIDIA#19749, NVIDIA#19585, NVIDIA#19766, NVIDIA#19963, NVIDIA#19588, NVIDIA#19600, NVIDIA#19825, NVIDIA#19821,
NVIDIA#19930, NVIDIA#18485.

Signed-off-by: Vasanth Sabavat <vsabavat@nvidia.com>
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