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[None][perf] Enable tiled FP8 context FMHA for head_dim 256 on SM120 - #19825
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Included review availability: This review used your included allowance. Your plan provides up to 12 included reviews per hour; 11 remain after this review. WalkthroughThe FMHA kernel enumerator adds an SM120 tiled configuration for head size 256. The runner routes SM120/SM121 E4M3 cases through tiled-kernel selection. The setup file updates its copyright range through 2026. ChangesSM120 FMHA kernel selection
Priority: ➖ Normal Estimated code review effort: 2 (Simple) | ~10 minutes Change: Feature Suggested reviewers: Merge Risk: ⚪ Minimal · up to No specific user-impacting issue was established in the changed kernel-selection path; unsupported configurations retain the unfused fallback. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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Signed-off-by: Anurag Mukkara <134339030+amukkara@users.noreply.github.com>
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Main's NVIDIA#19896 (2681ed1) moved PyTorchModelEngine's decoder execution into DecoderRunner (engine/runners/decoder/runner.py) and the encoder-decoder fast path into EncoderDecoderRunner, so this branch's model_engine.py changes conflicted. model_engine.py is main's; the branch's changes move to where that code now lives: - DecoderRunner, from NVIDIA#19816 (U1): the step-copy gather, the staged previous batch / position indices, gather_ids written by copy_to_device_if_changed, no num_accepted_draft_tokens buffer, and the CUDA graphs' static inputs; from NVIDIA#19814 (U3): the gather of vocabulary-sharded logits for post-processors. - EncoderDecoderRunner: its previous_batch_indices_cuda write clears the staged batch indices. - The two tests that called the moved members call the runner. Main's other commits since f891b3d: NVIDIA#19484, NVIDIA#19892, NVIDIA#19409, NVIDIA#19553, NVIDIA#19957, NVIDIA#19749, NVIDIA#19585, NVIDIA#19766, NVIDIA#19963, NVIDIA#19588, NVIDIA#19600, NVIDIA#19825, NVIDIA#19821, NVIDIA#19930, NVIDIA#18485. Signed-off-by: Vasanth Sabavat <vsabavat@nvidia.com>
Description
Use tiled fmha_v2 kernel for FP8 (E4M3) context attention with head_dim 256 on SM120/SM121. Targets nvidia/Qwen3.6-35B-A3B-NVFP4 which uses FP8 KV cache.
cpp/kernels/fmha_v2/setup.py: add a tiled64x128QMMA kernel for head_dim 256, alongside the existing non-tiled64x32kernel.fmhaRunner.cpp: restrict the forced non-tiled FP8 selection to SM89, so SM120/SM121 use the existing head-size heuristic, which selects tiled kernels for head_dim >= 256.Performance
fmha_v2 harness on RTX PRO 6K BSE, FP8 Q/K/V, head_dim 256, tiled vs non-tiled kernel.
The tiled kernel is faster on all 35 shapes tested: 2.03x - 3.52x, geomean 3.01x.
Test Coverage
The tiled kernel passes the fmha_v2 harness reference check on SM120 (
-epsilon 0.2) for paged KV and packed QKV; causal, padding, sliding-window and custom masks; ALiBi; GQA; chunked prefill; and FP8 and BF16 output.e2e accuracy verified by
tests/integration/defs/accuracy/test_llm_api_pytorch.py::TestQwen3_6_35B_A3B::test_nvfp4_w4a16Dev Engineer Review
setup.pyadds an SM120-only tiled64x128QMMA configuration for FP8 E4M3 with head_dim 256.fmhaRunner.cpplimits forced non-tiled FP8 selection to SM89, allowing SM120/SM121 to use the existing tiling heuristic. The reported benchmark and accuracy results are author-reported; no test execution results were provided.QA Engineer Review
No test changes.
Per-File QA Perspective
cpp/kernels/fmha_v2/setup.py: Adds a tiled-kernel configuration for SM120 and head_dim 256. QA should verify kernel selection and output correctness for supported shapes.cpp/tensorrt_llm/kernels/contextFusedMultiHeadAttention/fmhaRunner.cpp: Changes FP8 E4M3 kernel selection for SM120/SM121. QA should verify that the tiling heuristic selects the expected kernel and preserves output correctness.PR Checklist
Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
Test cases are provided for new code paths (see test instructions)
If PR introduces API changes, an appropriate PR label is added - either
api-compatibleorapi-breaking. Forapi-breaking, includeBREAKINGin the PR title.Any new dependencies have been scanned for license and vulnerabilities
CODEOWNERS updated if ownership changes
Documentation updated as needed
Update tava architecture diagram if there is a significant design change in PR.
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Please check this after reviewing the above items as appropriate for this PR.
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