[TRTLLM-15316][fix] SM107 FP8 GEMM routing and runtime guards (follow-up to #17485) - #18612
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Included review availability: Your plan provides up to 12 included reviews per hour; 11 remain after this review. WalkthroughThe changes extend architecture-aware dispatch for SM100-family and SM107 devices. They add SM107 kernel guards and MoE tactic fallback handling, preserve tensor-parallel mapping settings, and update related tests and reference-model behavior. ChangesGPU architecture updates
Estimated code review effort: 3 (Moderate) | ~25 minutes Merge Risk: ⚪ Minimal · up to This change adds SM107-aware dispatch, fallbacks, and explicit unsupported-operation errors while preserving existing behavior on other architectures. No concrete current-head merge-blocking risk remains. Suggested reviewers: 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
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In
`@tests/unittest/_torch/thop/parallel_hw_agnostic/test_cuda_tile_custom_ops.py`:
- Line 102: Add a dedicated test that runs on SM107 without the skip_rubin
decorator and directly verifies the rejection behavior of the affected CUDA
custom-operation functions. Keep the existing broader tests unchanged and assert
the expected failure for SM107.
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cpp/tensorrt_llm/kernels/weightOnlyBatchedGemv/kernelLauncher.htensorrt_llm/_torch/attention_backend/sparse/dsa/indexer.pytensorrt_llm/_torch/attention_backend/sparse/rocket/kernels.pytensorrt_llm/_torch/attention_backend/trtllm.pytensorrt_llm/_torch/custom_ops/cuda_tile_custom_ops.pytensorrt_llm/_torch/custom_ops/torch_custom_ops.pytensorrt_llm/_torch/modules/gated_mlp.pytensorrt_llm/_torch/modules/linear.pytensorrt_llm/_torch/modules/mlp.pytensorrt_llm/quantization/functional.pytests/unittest/_torch/custom_ops/test_moe_runner.pytests/unittest/_torch/moe/quantize_utils.pytests/unittest/_torch/thop/parallel_hw_agnostic/test_cuda_tile_custom_ops.py
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cute_dsl_fp8_gemm_blackwell only has cubins for sm100/103. Other sm_100f GPUs (e.g. sm107) must fall through to fp8_swap_ab_gemm, which needs the e8m0 + layout transform applied in transform_weights(). Previously, is_sm_100f() alone gated the cute_dsl path, so sm107 with use_cute_dsl_blockscaling_mm/disable_deep_gemm set would call an op with no cubins for that arch, and transform_weights() would skip the layout transform fp8_swap_ab_gemm needs. Signed-off-by: Faraz Khoubsirat <58580514+farazkh80@users.noreply.github.com>
…7 unit-test scope kernelLauncher.h dispatched W4A8/int8/int4 groupwise and per-channel kernels only for arch == 100 || arch == 103, and preprocess_weights_for_mixed_gemm() skipped weight interleaving only for sm_ == 100 || sm_ == 103 -- both leaving sm107 on the wrong path. Route both through the existing isSM100Family()/is_sm_100f() helpers, which already cover the sm100 family (100 <= sm < 110). Also bump triton_bmm's num_warps to 8 on sm107, matching its wider warp occupancy versus sm100/103. The cutlass_preprocessors and fpA_intB C++ hunks of the original fix are already covered by NVIDIA#17485. Signed-off-by: Faraz Khoubsirat <58580514+farazkh80@users.noreply.github.com> Co-authored-by: Yifei Zhang <219273404+yifeizhang-c@users.noreply.github.com>
…ridden-TP sub-Mapping GatedMLP and MLP build a smaller sub-Mapping when overridden_tp_size is set, but omitted enable_attention_dp, so it silently reset to the Mapping default instead of following the parent mapping. Arch-neutral: any model path constructing an overridden-TP MLP with attention DP enabled is affected. Signed-off-by: Faraz Khoubsirat <58580514+farazkh80@users.noreply.github.com>
MoeGemmRunner appends SM80-style grouped-GEMM tactics after its TMA-WS tactics. On sm107 bf16xbf16, the first SM100 TMA-WS tactic can fail to initialize, so an autotuner miss (tactic == -1) must resolve to the runner's final (shape-safe SM80-style) tactic instead. Gated to sm107 + bf16 x bf16; every other arch/dtype combination is unchanged. Signed-off-by: Faraz Khoubsirat <58580514+farazkh80@users.noreply.github.com> Co-authored-by: Bowen Fu <BowenFu@users.noreply.github.com>
cuda_tile_rms_norm and cuda_tile_rms_norm_fuse_residual_ have no CUDA Tile kernels built for sm107 and were silently falling through to undefined behavior instead of failing loudly. Raise RuntimeError up front, and skip the corresponding unit tests on sm107 via the existing skip_rubin marker. Signed-off-by: Faraz Khoubsirat <58580514+farazkh80@users.noreply.github.com> Co-authored-by: Yifei Zhang <219273404+yifeizhang-c@users.noreply.github.com>
…m ops CodeRabbit review: the existing tests skip SM107 entirely (@skip_rubin), so the RuntimeError guard added for that arch had no test exercising it. Add two tests that monkeypatch get_sm_version() to 107 and assert the ops raise, without needing SM107 hardware. Signed-off-by: Faraz Khoubsirat <58580514+farazkh80@users.noreply.github.com>
…e trtllm-gen FP8 block-scale GEMM Review feedback on this PR: routing every sm_100f GPU outside sm100/103 to fp8_swap_ab_gemm made disable_deep_gemm a silent no-op on sm107 -- fp8_swap_ab_gemm is the DeepGEMM path, and models set that flag for DeepGEMM correctness bugs (Qwen3 accuracy, EXAONE4 illegal memory access). Instead, when use_cute_dsl_blockscaling_mm or disable_deep_gemm is set on an sm_100f GPU that is not sm100/103, use fp8_block_scaling_gemm: its sm100-family branch is the trtllm-gen kernel, which has sm107 cubins and consumes the same raw fp32 scales as the CuTe DSL path. Warn once when use_cute_dsl_blockscaling_mm falls through, since there the requested kernel is genuinely unavailable. transform_weights() no longer needs an sm gate: both non-DeepGEMM paths consume raw scales, so main's original condition is correct as-is. Signed-off-by: Faraz Khoubsirat <58580514+farazkh80@users.noreply.github.com>
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Re-reviewed the SM107 disable_deep_gemm edge case. On non-100/103 SM100f devices the opt-out now routes through fp8_block_scaling_gemm rather than the DeepGEMM path, while explicit CuTe DSL requests warn about the fallback. My previous blocker is resolved.
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Description
Follow-up to #17485 ("[TRTLLM-15316][feat] sm107 gemm + quant"). That PR shipped the C++-only
slice; this one lands the Python wiring that goes with it: SM107 FP8 GEMM routing correctness, a
couple of
arch == 100 || arch == 103sites that should use the existingisSM100Family/is_sm_100fhelpers, two arch-neutral bugfixes that ride along, and a couple ofsmall SM107-gated runtime guards.
A separate CuTe DSL PR is coming next that adds the FP8 CuTe DSL GEMM/BMM runners for SM107 — none
of that is included here.
Credits: items 2 and 5 below were originally authored by Yifei Zhang and item 4 by Bowen Fu
(
Co-authored-bytrailers on those commits).Scope
tensorrt_llm/_torch/modules/linear.py,tests/unittest/_torch/moe/quantize_utils.py) —cute_dsl_fp8_gemm_blackwellruns only onsm100/103. When
use_cute_dsl_blockscaling_mmordisable_deep_gemmis set on anothersm_100fGPU (e.g. sm107), route to
fp8_block_scaling_gemminstead: its sm100-family branch is thetrtllm-gen kernel, which has sm107 cubins and consumes the same raw fp32 scales as the CuTe DSL
path — so
disable_deep_gemmkeeps meaning "not DeepGEMM" (Qwen3 / EXAONE4 set it for DeepGEMMcorrectness issues). A one-time warning is logged when
use_cute_dsl_blockscaling_mmfallsthrough, since the requested kernel is genuinely unavailable there.
transform_weights()isunchanged: both non-DeepGEMM paths consume raw scales, so main's existing condition already
matches.
isSM100Family/is_sm_100fconsistency (cpp/tensorrt_llm/kernels/weightOnlyBatchedGemv/kernelLauncher.h,tensorrt_llm/_torch/attention/backends/sparse/rocket/kernels.py,tensorrt_llm/quantization/functional.py) —residue of an already-merged fix (the cutlass_preprocessors/fpA_intB C++ hunks landed in [TRTLLM-15316][feat] sm107 gemm + quant #17485;
this is the remaining Python + one C++ dispatch site).
enable_attention_dppropagation into overridden-TP sub-Mapping(gated_mlp.py,mlp.py) —arch-neutral bugfix, nvbugs/6568929.
custom_ops/torch_custom_ops.pyMoERunner._resolve_fallback_tactic) —gated to sm107 + bf16 x bf16; falls back to the runner's shape-safe final tactic when the autotuner
has no cached tactic (
tactic == -1).custom_ops/cuda_tile_custom_ops.py) — no CUDA Tile kernels arebuilt for sm107; raise
RuntimeErrorinstead of silently running undefined behavior, and skip thecorresponding unit tests on sm107.
Blast radius
modules/linear.py(apply)use_cute_dsl_blockscaling_mm or disable_deep_gemmbranch:sm_version in (100, 103)→ CuTe DSL, else → trtllm-genfp8_block_scaling_gemmfp8_swap_ab_gemmbranch and the SM90/SM120 paths are untouchedkernelLauncher.hisSM100Family(arch)(100 <= arch < 110)attention/backends/sparse/rocket/kernels.py(triton_bmm)get_sm_version() == 107picksnum_warps=8num_warps=4(unchanged)quantization/functional.py(preprocess_weights_for_mixed_gemm)is_sm_100f(sm_)(100 <= sm < 110)gated_mlp.py,mlp.pyMappingnow correctly inheritsenable_attention_dpfrom the parent mapping instead of resetting itcustom_ops/torch_custom_ops.py(MoERunner)get_sm_version() == 107 and x_dtype == weight_dtype == bfloat16_resolve_fallback_tacticis a no-op passthroughcustom_ops/cuda_tile_custom_ops.pyget_sm_version() in [107]Test coverage
SM107 hardware doesn't exist to test on directly, so verification here is: (a) the new/changed unit
tests, and (b) a B300 (sm100/103, Blackwell) regression pass confirming every touched path is an
exact no-op off SM107, run against a local build of this branch (
--cuda_architectures=103-real):tests/unittest/_torch/moe/test_moe_runner.py(new) — 6/6 passed. CoversMoERunner._resolve_fallback_tactic: sm107+bf16 fallback, all other arch/dtype combinations asno-ops, tuned-tactic passthrough.
tests/unittest/_torch/thop/parallel_hw_agnostic/test_cuda_tile_custom_ops.py— 229/229 passed onB300. The
@skip_rubinmarkers only skip on sm107, so the existing 227 are a full regression run forthe guard's else-branch; the 2 new
*_rejects_sm107tests monkeypatchget_sm_version()to 107 andassert both ops raise, covering the guard itself without SM107 hardware.
tests/unittest/_torch/modules/test_linear_uneven_tp.py::TestFP8BlockScalesMLP— 3/3 passed onB300. Exercises both the
linear.pyFP8 routing fix and theenable_attention_dpsub-Mappingfix end to end.
fp8_quantize_1x128+fp8_block_scaling_gemm, raw scales) ismain's existing
test_fp8_block_scale_gemmpath; its body passes on B300 for(m,k,n) ∈ {(128,7168,2112), (7,1536,24576), (4096,2048,7168), (64,1024,1024)}(
calc_diff < 1e-3,assert_close(atol=rtol=1e-3)). The test's own sm list already includes 107.tests/unittest/_torch/thop/parallel/test_weight_only_quant_gemm.py+test_weight_only_quant_linear.py— 68/68 passed on B300. Exercises thekernelLauncher.hisSM100Familydispatch.tests/unittest/_torch/moe/test_moe_module.py -k FP8BlockScales— 17 passed / 78 skipped(hardware-gated variants) on B300. Exercises
RefMLPFusedMoE.post_load_weights().Not independently verifiable pre-merge: the sm107-only branches themselves (routing to
fp8_swap_ab_gemm, thenum_warps=8triton config, the MoE fallback tactic, the CUDA TileRuntimeError, and the relaxed sm107 accuracy tolerance inquantize_utils.py) — there's no SM107hardware to run them on. These are covered by code review and by the mock-based
test_moe_runner.pycases that forceget_sm_version() == 107.Checklist
disclosure_gate.shexit 0; every added comment read manually-s), committer is the noreply identity, original authors preserved via--author=Note: CI (
/bot run) is triggered manually by Faraz, not automated for this PR.[x] Please check this after reviewing the above items as appropriate for this PR.
Dev Engineer Review
fp8_block_scaling_gemmwhen required.isSM100Familyandis_sm_100ffor architecture checks.enable_attention_dpin overridden tensor-parallel mappings.RuntimeError.transform_weights()behavior.QA Engineer Review
Modified test functions include:
-1for unsupported architectures and dtype combinations.The summary does not identify matching entries in
tests/integration/test_lists/,test-db/, orqa/. Coverage registration requires follow-up.Verdict: needs follow-up.