[https://nvbugs/6525059][fix] 128KiB-align TMA-OOB MoE workspace buffers on Blackwell - #18133
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Included review availability: Your plan provides up to 12 included reviews per hour; 11 remain after this review. WalkthroughThe FP8 block-scale MoE path now uses aligned intermediate buffers with tail headroom and passes their pointers through the workspace. Five platform-specific integration test waivers are removed. ChangesFP8 MoE buffer alignment
Estimated code review effort: 3 (Moderate) | ~20 minutes Merge Risk: ⚪ Minimal · up to This localized change aligns and pads Blackwell MoE workspace buffers to prevent illegal-memory accesses, with targeted regression coverage; no actionable merge-blocking risk remains beyond normal checks and review. Suggested reviewers: 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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Could you help to add a corresponding test case in the test_moe_backend.py? |
…ers on Blackwell The FP8 block-scale MoE GEMM kernels drive their A/B/C loads/stores through the "rgTma" TMA-OOB descriptors, which on Blackwell (sm100/sm103) run in OOB_ADDR_GEN_MODE_BASE_128kB: the reshaped descriptor's addressable space is >= 128 KiB, so the TMA unit may probe up to a 128 KiB-aligned boundary past the descriptor base even though software never reads there. The backing workspace must therefore start 128 KiB-aligned and own >= 128 KiB of mapped memory after that base. maybeGetMinTokenCount already sizes gemm1_output / activation_output / gemm2_output to >= 128 KiB, but at::detail::empty_cuda returns 512 B-aligned slices of a shared caching-pool block, so a workspace that lands near a pool-block end lets the 128 KiB-mode OOB probe cross into an unmapped neighbor, giving a sporadic cudaErrorIllegalAddress during warmup / small-decode batches (tile_tokens_dim 8 and 16). This is the same Blackwell TMA-OOB family as NVBug 5435459; the trtllm-gen test harness dodges it by allocating dedicated 128 KiB-padded cudaMalloc buffers. Allocate the three rgTma workspace buffers 128 KiB-aligned with 128 KiB tail headroom. Scaling-factor buffers are unaffected (DeepSeek-FP8 loads them via LDGSTS, not the TMA-OOB path). This also resolves NVBug 6602176 (the tileN=16 dsFp8 GEMM2 illegal memory access on sm103 for num_tokens<=8 && intermediate_size<=512), which is the same OOB_ADDR_GEN_MODE_BASE_128kB root cause; its failing case (test_moe_backend ... quant=FP8_BLOCK_SCALES) runs through the same fp8BlockScaleMoe.cpp path. Unwaive the now-fixed tests: - accuracy/test_llm_api_pytorch.py::TestQwen3_30B_A3B::test_dummy_load_format (B200/B300/GB200/GB300, nvbugs/6525059) - unittest/_torch/modules/moe/test_moe_backend.py::test_moe_backend -k "TRTLLM" (nvbugs/6602176) Signed-off-by: Qingqing Gai <qgai@nvidia.com>
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The exact failing case for nvbugs/6602176 already exists in test_moe_backend.py |
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Description
On Blackwell (SM100/SM103) the FP8 block-scale MoE GEMM kernels drive their A/B/C loads/stores through the
rgTmaTMA-OOB descriptors, which run inOOB_ADDR_GEN_MODE_BASE_128kB: the reshaped descriptor's addressable space is >= 128 KiB, so the TMA unit may probe up to a 128 KiB-aligned boundary past the descriptor base even though software never reads there. The backing workspace must therefore start 128 KiB-aligned and own >= 128 KiB of mapped memory after that base.maybeGetMinTokenCountalready sizesgemm1_output/activation_output/gemm2_outputto >= 128 KiB, butat::detail::empty_cudareturns 512 B-aligned slices of a shared caching-pool block. A workspace that lands near a pool-block end lets the 128 KiB-mode OOB probe cross into an unmapped neighbor, giving a sporadiccudaErrorIllegalAddressduring warmup / small-decode batches (tile_tokens_dim8 and 16). Same Blackwell TMA-OOB family as NVBug 5435459; the trtllm-gen test harness dodges it by allocating dedicated 128 KiB-paddedcudaMalloc.Fix: allocate the three
rgTmaworkspace buffers 128 KiB-aligned with 128 KiB tail headroom. Scaling-factor buffers are unaffected (DeepSeek-FP8 loads them via LDGSTS).Resolves NVBug 6525059 (tileN=8) and NVBug 6602176 (tileN=16, same root cause; its failing case
test_moe_backend ... quant=FP8_BLOCK_SCALESruns the samefp8BlockScaleMoe.cpppath).Root-cause evidence
cp.async.bulk.tensor(GEMM2 activation load), coords valid.Xid 31 ... GPCCLIENT_T1 ... FAULT_PDE VIRT_READat 128 KiB-aligned addresses.ptr%128KiB=91136(misaligned) inoob128kMode=1; after the fix everyrgTma(dim=4) descriptor is 128 KiB-aligned and the run passes with no new Xid 31.Test Coverage
accuracy/test_llm_api_pytorch.py::TestQwen3_30B_A3B::test_dummy_load_format— unwaived on B200/B300/GB200/GB300 (was nvbugs/6525059).unittest/_torch/modules/moe/test_moe_backend.py::test_moe_backend -k "TRTLLM"— unwaived (was nvbugs/6602176).Follow-ups (not in this PR)
fp4BlockScaleMoe.cpp,mxFp4BlockScaleMoe.cpp,fp8PerTensorScaleMoe.cpp(same allocation pattern, same latent TMA-OOB exposure).Dev Engineer Review
rgTmaworkspace buffers for Blackwell FP8 block-scale MoE GEMM.QA Engineer Review
TestQwen3_30B_A3B::test_dummy_load_format.