[TRTLLM-15740][perf] VisualGen Wan: deduplicate shared RoPE SMEM staging - #18036
[TRTLLM-15740][perf] VisualGen Wan: deduplicate shared RoPE SMEM staging#18036yanxinzhangcs wants to merge 2 commits into
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Stage one shared FP32 cosine and sine row per token instead of replicating it across heads. Preserve the existing BF16 and per-head layouts and cover both RoPE styles with exact layout-parity tests. Signed-off-by: Yanxin Zhang <yanxinz@nvidia.com>
Signed-off-by: Yanxin Zhang <yanxinz@nvidia.com>
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@coderabbitai summary
Description
Closes #18035.
The full-dimension fused DiT QK-norm/RoPE kernel currently expands a shared FP32 cosine/sine row across every head in dynamic shared memory. Wan A14B uses one
head_dim=128row shared by 40 heads, so the expansion moves and reserves data that every head reads identically.This change:
head_dim;No public API, mathematical algorithm, or architecture-specific dispatch is added. The existing generic dispatch remains in place for every layout and architecture.
This is a focused optimization of the current two-row full-dimension kernel introduced in #13985 and routed to Wan by the unified dispatch in #14529. The earlier #13052 cross-head path was separate and was removed by #14529.
Attribution
The initial optimization idea, prototype, and B200 research measurements were contributed by @chang-l. This PR reshapes that work into a shared-FP32-only upstream change with explicit fallbacks and layout-parity coverage.
Performance and quality evidence
Exact upstream candidate
Candidate commit:
6507727246e91e80855d398694e8bd4a585610e1.40x128, shared FP32, interleaved)<128,true,false,float>, 43,072 B dynamic SMEM,STACK=LOCAL=0, noLDL/STL, and the pinned two-call internal rsqrt topology<128,true,true,float>, 122,944 B dynamic SMEM,STACK=LOCAL=0, noLDL/STL, and the same canonical call/return skeleton; a direct return or one adjacent preserved-link register bridge is allowedDo not substitute the research data below for these candidate-specific gates. Build-only diagnostics on the identical source diff passed the source/tree gate, full SM100 build, 6/6 new tests, 11/11 existing focused tests, and the profiled dispatch test. They reported candidate
REG93/STACK0/LOCAL0at 43,072 B dynamic SMEM and expanded controlREG95/STACK0/LOCAL0at 122,944 B, with noLDL/STLin either focused SASS body. The first diagnostic validator incorrectly rejected any compiler-generated internalCALL; its successor then incorrectly required a direct return-register match and rejected the control specialization's valid one-hop return bridge. These runs are diagnostic evidence, not passing receipts. The final fetchable commit must pass the corrected dual-role gate before review.Earlier research prototype (directional only)
Measured by @chang-l on B200; this was not the final upstream diff.
The research parity check reported a bitwise-identical full QKV output.
The same research sweep measured LB2 at 504 us and LB3 at 486.98 us, while LB4/LB5 regressed to 542/611 us. The final candidate deliberately carries no launch bound; these sweep points are directional context, not its performance result.
A superseded research prototype included the launch-bound specialization and
also changed shared-BF16 staging. It is not the PR patch. The proposed diff is
FP32-only, keeps the BF16 layout unchanged, and is the only source candidate
covered by the pending gates.
Test Coverage
test_full_dim_shared_fp32_cos_matches_expandedcompares shared FP32 embeddings against materialized per-head embeddings withrtol=0,atol=0for:(num_heads, head_dim) = (24, 64), (24, 128), (40, 128); andPR Checklist
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