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[None][perf] Address inter-iter idle times
- #16875
#16875
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pcicotti
merged 10 commits into
NVIDIA:feat/m3_with_msa
NVIDIA/TensorRT-LLM:feat/m3_with_msa
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brb-nv:user/brb/address-inter-iter-delays-redo
brb-nv/TensorRT-LLM:user/brb/address-inter-iter-delays-redo
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Jul 26, 2026
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[None][perf] Address inter-iter idle times
#16875
pcicotti
merged 10 commits into
NVIDIA:feat/m3_with_msa
NVIDIA/TensorRT-LLM:feat/m3_with_msa
from
brb-nv:user/brb/address-inter-iter-delays-redo
brb-nv/TensorRT-LLM:user/brb/address-inter-iter-delays-redo
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Commits
Commits on Jul 26, 2026
[None][perf] Build MSA block ids into a single pinned buffer
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[None][perf] Build the MSA page table on the host
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[None][perf] Vectorize MSA out_cache_loc and drop the req_to_token D2H
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[None][perf] Stage MSA host mirrors through pinned memory
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[None][perf] Remove host syncs from the MSA sparse plan builder
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[None][fix] Drop the stale MSA eager empty-block short-circuit
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[None][fix] Clamp corrected MSA kv_lens to the prepared extent
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[None][perf] Remove the blocking D2H from MSA on_update_kv_lens
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[None][fix] Patch the length MSA sparse plans actually mask with
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[None][fix] Repair the MSA run_indexer test fakes
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