remove dead manual_release_grads code path in 1F1B overlap schedule - #4511
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asolergi-nv merged 3 commits intoMay 14, 2026
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`ScheduleNode.manual_release_grads` was hardcoded to False at construction and never reassigned anywhere in the codebase, so the two `if self.manual_release_grads:` branches in `ScheduleNode._backward` and `TransformerLayerNode.backward_dw` were unreachable. The supporting bookkeeping — `self.delay_grads_release`, `self.output_grads`, the `assert self.delay_grads_release` in `backward_dw`, and the `if self.delay_wgrad_compute: self.output_grads = grads; ...` block in `backward_impl` — existed only to feed the unreachable branches. PyTorch's caching allocator already reclaims the dgrad tensors when the last Python reference drops at the end of `_backward` / `backward_dw`, so this whole machinery was a no-op. A/B comparison with the flag temporarily exposed as a TransformerConfig field (qwen3_moe_proxy, PP=1 EP=8, overlap_moe_expert_parallel_comm + delay_wgrad_compute, 100 iters on real 8xH100): peak max-allocated memory was identical at 12479.13 MB with the flag both ON and OFF.
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/ok to test 876f049 |
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🔄 Merge queue validation started! You can track the progress here: https://github.com/NVIDIA/Megatron-LM/actions/runs/25852953881 |
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…apping_main Conflict resolution + porting upstream deltas to relocated code: - gpt/fine_grained_callables.py: keep slim HEAD; PreProcess / PostProcess / TransformerLayerNode / _BackwardDWWrapper and build_mtp_layer_callables / build_layer_callables now live under common/. - common/utils.py: port PR NVIDIA#4511 (remove dead manual_release_grads code path) into TransformerLayerNode.backward_impl / backward_dw. - common/fine_grained_callables.py: port PR NVIDIA#2645 (packed sequence GDN) into build_mtp_layer_callables — unpack the new 5-tuple from _get_embeddings and forward packed_seq_params / padding_mask. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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…VIDIA#4511) Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com>
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…VIDIA#4511) Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com>
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…VIDIA#4511) Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com> Signed-off-by: yhgalaxy <yhgalaxy@outlook.com>
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…VIDIA#4511) Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com> Signed-off-by: Jon Barker <jbarker@aws-cmh-slurm-1-vscode-02.cm.cluster>
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…VIDIA#4511) Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com>
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…VIDIA#4511) Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com> Signed-off-by: Dmytro Pykhtar <dpykhtar@nvidia.com>
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What does this PR do ?
Removes dead code in the 1F1B overlap schedule.
ScheduleNode.manual_release_gradswas hardcoded toFalseat construction inpipeline_parallel/utils.pyand never reassigned anywhere in the codebase, so bothif self.manual_release_grads:branches were unreachable. The supporting bookkeeping (delay_grads_release,output_grads) existed only to feed those unreachable branches.Removed:
pipeline_parallel/utils.py:self.manual_release_grads = Falseandself.delay_grads_release = Falsefields onScheduleNode; the unreachableg.untyped_storage().resize_(0)branch in_backward.models/gpt/fine_grained_callables.py: inbackward_impl, theif self.delay_wgrad_compute: self.output_grads = grads; self.delay_grads_release = ...block (only consumed by the dead release path); inbackward_dw, the unreachabletensor.untyped_storage().resize_(0)loop, the now-meaninglessassert self.delay_grads_release, and the explicitself.output_grads = Noneclearing.PyTorch's caching allocator already reclaims the dgrad tensors when the last Python reference drops at the end of
_backward/backward_dw, so this whole machinery was a no-op. Same scope as #4122.Why this is safe
A/B comparison was run with the flag temporarily exposed as a
TransformerConfigfield, onqwen3_moe_proxy(PP=1 EP=8,overlap_moe_expert_parallel_comm+delay_wgrad_computeenabled, 100 iters on real 8×H100, EOS):manual_release_gradsFalse(status quo)True(release on)Peak allocated memory is identical to two decimals.
Companion dev PR: #4510
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