Fix assertion logic in combined_1f1b_schedule_for_interleaved_pipelining - #4276
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asolergi-nv merged 4 commits intoApr 28, 2026
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April 13, 2026 13:34
…ning The assert checked forward microbatch's `input_tensor` against backward microbatch's `input_tensor_grad`. In interleaved PP with VP>1, backward has chunk reversal (`model_chunk_id = num_chunks - id - 1`), so forward and backward are always on different VP stages in steady-state. This causes false assertion failures when forward is on a non-first stage (input_tensor != None) but backward is on a first stage (input_tensor_grad == None). Fix: check `b_input_tensor is not None` instead, which directly corresponds to whether the backward microbatch received activation from upstream and thus should produce input_tensor_grad. Reproduction: PP=2 VP=2 EP=4 TP=1 with --overlap-moe-expert-parallel-comm
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Phlip79
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/ok to test 4c8eb93 |
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LGTM. Both fixes are correct:
b_model_chunk_id is not Noneinstead of truthiness check — prevents skipping backward post-processing when chunk ID is 0.b_input_tensor is not Nonecorrectly guards theinput_tensor_gradassertion against the backward path's input tensor rather than the forward path's.
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/ok to test 3554b4c |
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🔄 Merge queue validation started! You can track the progress here: https://github.com/NVIDIA/Megatron-LM/actions/runs/25037413795 |
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…ing (NVIDIA#4276) Co-authored-by: Hanpeng Hu <haaanpeng@outlook.com> Co-authored-by: Deepak Narayanan <deepakn94@gmail.com> Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com>
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…ing (NVIDIA#4276) Co-authored-by: Hanpeng Hu <haaanpeng@outlook.com> Co-authored-by: Deepak Narayanan <deepakn94@gmail.com> Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com> Signed-off-by: yhgalaxy <yhgalaxy@outlook.com>
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…ing (NVIDIA#4276) Co-authored-by: Hanpeng Hu <haaanpeng@outlook.com> Co-authored-by: Deepak Narayanan <deepakn94@gmail.com> Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com> Signed-off-by: Jon Barker <jbarker@aws-cmh-slurm-1-vscode-02.cm.cluster>
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…ing (NVIDIA#4276) Co-authored-by: Hanpeng Hu <haaanpeng@outlook.com> Co-authored-by: Deepak Narayanan <deepakn94@gmail.com> Co-authored-by: Antoni-Joan Solergibert <asolergibert@nvidia.com>
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Description
Fix incorrect assertion in
combined_1f1b_schedule_for_interleaved_pipeliningfunction at line 237.Issue
The assertion at line 237-238 checks:
However, this is logically incorrect. The
input_tensor_gradis the backward pass output that corresponds tob_input_tensor(backward input tensor), notinput_tensor(forward input tensor).Root Cause Analysis
input_tensoris set whenf_model is not None(forward model exists) at lines 186-192b_input_tensoris set whenb_model is not None(backward model exists) at lines 198-202input_tensor_gradis computed based onb_input_tensorat lines 436-447Fix
Change line 237 from:
to:
This ensures the assertion correctly validates that
input_tensor_gradis not None when the backward input tensor exists, matching the actual data flow.Type of change
Testing
The fix corrects the logical condition to match the data flow in the combined forward-backward step computation.