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Use torch.int64 for grad_num_zero accumulation - #4015

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deepakn94 merged 2 commits into
NVIDIA:mainfrom
WanZzzzzz:fix_acc
Mar 26, 2026
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Use torch.int64 for grad_num_zero accumulation#4015
deepakn94 merged 2 commits into
NVIDIA:mainfrom
WanZzzzzz:fix_acc

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What does this PR do ?

Currenly, the num_zero of gradient will be different when bucket size/layout is different. This due to FP32 accumulation error. Since num zero is accumulated in FP32 which has 23 mantissa bits, it can only distinguish 2^23 values between consecutive powers of 2. If accumulated num zero falls into  2^29 ~ 2^30 (1e9 scale), the spacing between consecutive representable FP32 values is 2^29 / 2^23 = 2^6 = 64, which means small per-grad zero count will be rounded away.

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Signed-off-by: qiyuw <qiyuw@nvidia.com>
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WanZzzzzz requested review from a team as code owners March 24, 2026 17:02
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svcnvidia-nemo-ci marked this pull request as draft March 24, 2026 17:02
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WanZzzzzz marked this pull request as ready for review March 24, 2026 17:02
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@svcnvidia-nemo-ci svcnvidia-nemo-ci added the Final Review PR is in the "final review" stage label Mar 24, 2026
@deepakn94 deepakn94 changed the title Increase representable range for num_zero accumulation Use torch.int64 for grad_num_zero accumulation Mar 25, 2026
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/ok to test 0956407

@svcnvidia-nemo-ci svcnvidia-nemo-ci added Approved All necessary approvals have been made and removed Final Review PR is in the "final review" stage labels Mar 25, 2026
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deepakn94 enabled auto-merge March 25, 2026 21:57
@svcnvidia-nemo-ci svcnvidia-nemo-ci added this to the Core 0.16 milestone Mar 25, 2026
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deepakn94 added this pull request to the merge queue Mar 26, 2026
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🔄 Merge queue validation started!

You can track the progress here: https://github.com/NVIDIA/Megatron-LM/actions/runs/23576675526

Merged via the queue into NVIDIA:main with commit a01a6c5 Mar 26, 2026
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yangbofun pushed a commit to xlm-research/Megatron-LM that referenced this pull request May 22, 2026
Signed-off-by: qiyuw <qiyuw@nvidia.com>
Co-authored-by: qiyuw <qiyuw@nvidia.com>
Co-authored-by: Deepak Narayanan <dnarayanan@nvidia.com>
yhgalaxy pushed a commit to yhgalaxy/Megatron-LM that referenced this pull request Jun 17, 2026
Signed-off-by: qiyuw <qiyuw@nvidia.com>
Co-authored-by: qiyuw <qiyuw@nvidia.com>
Co-authored-by: Deepak Narayanan <dnarayanan@nvidia.com>
Signed-off-by: yhgalaxy <yhgalaxy@outlook.com>
jon-barker pushed a commit to jon-barker/Megatron-LM that referenced this pull request Jul 10, 2026
Signed-off-by: qiyuw <qiyuw@nvidia.com>
Co-authored-by: qiyuw <qiyuw@nvidia.com>
Co-authored-by: Deepak Narayanan <dnarayanan@nvidia.com>
Signed-off-by: Jon Barker <jbarker@aws-cmh-slurm-1-vscode-02.cm.cluster>
terminator123 pushed a commit to 021ai/Megatron-LM that referenced this pull request Aug 3, 2026
Signed-off-by: qiyuw <qiyuw@nvidia.com>
Co-authored-by: qiyuw <qiyuw@nvidia.com>
Co-authored-by: Deepak Narayanan <dnarayanan@nvidia.com>
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6 participants