[MAIN][NVFP4] Support NVFP4 MOE with Proper Padding - #1985
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CUDA graph support will come in a separate MR? |
We cannot really capture the cuda graph for moe layers. Regarding more fine grained moe captures, main branch currently don't have many of them, while there is a PR that is trying to get those features into |
Yup, I meant everything apart from the MoE layers. |
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Rebased to latest main |
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This PR also bumps up align size of FP4 to 64 from 32 based on TE PR: NVIDIA/TransformerEngine#2351 |
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
…or MOE Co-authored-by: Zhongbo Zhu <zhongboz@nvidia.com>
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
Signed-off-by: Zhongbo Zhu <zhongboz@nvidia.com>
Signed-off-by: Xiaowei Ren <xren@nvidia.com>
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/ok to test 08141bb |
What does this PR do ?
Contributing NVFP4 MOE utils available in
devbranch back tomainas it has been validated with E2E training: b01ad5b[Already merged] TE dependency already available in TE main branch: NVIDIA/TransformerEngine#2215
TE PR for fused FP4 Grouped kernels want 64 aligned size in M, so also need to update accordingly in Mcore: NVIDIA/TransformerEngine#2351
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