perf(vllm): batch MXFP8 MoE refit shuffles - #3478
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Final validation for Matched 20-step A/BQwen3-30B-A3B MXFP8 on 8 OCI-HSG GB200 nodes / 32 GPUs with NCCL Reshard. Both arms used source
Step 11 lacks the transfer/update metric in both logs. Both jobs recorded and synced all 20 steps. After training, both hit the same unrelated Ray Python-finalization assertion and exited Regression and CI evidence
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Should this behavior be derived from the selected backend rather than exposed as a user-facing knob? Both branches produce the FlashInfer TRTLLM layout, so setting |
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For the other parts, looks reasonable to me. |
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…e-split Signed-off-by: seonjinn <sna@nvidia.com>
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@youngeunkwon0405 Thank you so much for your time and for reviewing this PR, Youngeun! |
What does this PR do?
This PR extracts the MXFP8 MoE layout-transform optimization from #3294 into an independently reviewable change.
The optimization is transport-independent and does not modify weight-transfer metadata or precision negotiation. BF16-training/MXFP8-rollout support and the required vLLM 0.25.1 MXFP8 MoE kernel lifecycle are owned by #3477. The current branch temporarily retains the lifecycle block so it remains testable against
main; it will be removed by rebasing after #3477 merges. The final #3478 diff will contain only the batched-shuffle optimization and its tests.Why?
Each MoE layer has W13 and W2 value tensors plus their E8M0 scale tensors. The reference path launches the same four value-dependent row shuffles once per expert. Stacking experts preserves the exact row permutation while reducing Python dispatch and kernel-launch overhead.
The resulting layout is specific to
Fp8MoeBackend.FLASHINFER_TRTLLM. Selecting another backend now fails before mutating weights rather than silently applying the FlashInfer layout.Performance
Matched Qwen3-30B-A3B MXFP8, 8-node/32-GPU GB200, 20-step NCCL-Reshard A/B. Both arms used source
9706cdc, the same container, runtime, topology, rollout schedule, and instrumentation; only the shuffle implementation changed. Values are arithmetic means over Steps3-9,11-19.n=15)Step 11 lacks the transfer/update metric in both logs. The non-refit workload phases remained within 0.85%, and mean generation length was identical. Reference: job
5884885, W&B. Batched: job5883555, W&B.Correctness
CUDA tests compare the batched output bitwise with the per-expert reference for gated aligned shapes, gated shapes requiring scale padding, and non-gated MoE shapes. Tests also verify backend-derived dispatch, explicit rejection of unsupported backends, stable runtime parameter objects and storage across refits, and no caller-retained gather output buffers.