How to get multiple I/O port outputs like 0x80, 0x81, 0x82, 0x83

[hanetzer]

Hello. So, I'm doing some tinkering with a ryzen motherboard (Asrock X370 Killer Sli A/C with a ryzen 3200g)
in relation to the coreboot project. Maybe it will go somewhere, maybe not.
In any case, these machines have a 32-bit post code system, which are output to ports 0x80-0x83.
How much issue would it be to be able to sample a 'range' of io ports with this hardware setup?

[hanetzer]

changing the 0x80 to either of the other ports 'works' but I've no idea how to get all of it working that way,
and would be a great help to my current project.
so an ideal readout would be 0x83:0x82:0x81:0x80's data, in that order.

[MrGreensWorkshop]

Hi, As you already know, the implementation allows you to use only one port at a time.

There are several approaches to achieving this. (ish..)

1. I actually explained how the PIO program works here,
   There is a part that gets the address and checks if it matches the input address.

check out the #4 (comment)

2. Since the Raspberry Pi Pico has two PIOs, one more I/O port can be implemented. 2 ports at most. For 4 I/O ports, you can use 2 Raspberry Pi Picos that are connected to the LPC bus. Also, PIO doesn't allow you to use the same pins, so LED pins should be changed. (If you don't use LEDs, just ignore this.)

3. Exporting I/O addresses to GPIOs, checking with logic ICs (like ISA cards), and inputting that result to the PIO. The thing is, we need time between clocks. I'm not sure if there is a time to do this.

I think that's all I can say. Good luck.

[MrGreensWorkshop]

I did some debugging. Filtering 0x8X works, but it still doesn't give you the address as output, which is not acceptable. I managed to get the filter working and getting the last address as output, so I'm putting it in a branch.

[MrGreensWorkshop]

I put the working code on this branch.

This is the log output

STARTED
initializing the lpc bus sniffer program
Filter: 0x80020000
program loaded at 1, sm: 0
System clock is 264000 kHz
Starting to sample the POST codes.
...
...
data: 0x92180020
...
data: 0x12080020

on Linux

# Write 0x92 to address 0x81 (129)
~# echo -e "\x92" | dd of=/dev/port bs=1 count=1 seek=129

serial output : data: 92 18 00 20
92 -> 0x92 data
18-> 0x81 address (swapped nibbles)

# Write 0x12 to address 0x80 (128)
~# echo -e "\x12" | dd of=/dev/port bs=1 count=1 seek=128

serial output : data: 12 08 00 20
12 -> 0x12 data
08-> 0x80 address (swapped nibbles)

[hanetzer]

yes this works quite well. Takes a bit of post-processing to make sense of the data (generally the firmware seems to write port 0x80 thru 0x83, in that order, in sequence) but this appears to dump most of it. So it seems my boot failure is happening due to a null pointer, thanks a lot.

[MrGreensWorkshop]

I'm glad to help you diagnose the problem. I hope you can fix it. Thanks for the info about byte order, in case I dive into coreboot.

[hanetzer]

I can't say this is true for all boards, but it is the observed behavior of this as seen
through a logic analyzer, and possibly all ryzen machines.

[MaryJosephine123]

Our testing platform has a 4-digit 7 segment LED display for displaying the post code. The first two digits are from port 81, and the last two digits are from port 80. Using this github (git clone https://github.com/MrGreensWorkshop/RasPiPicoSDK-PicoBiosPostCodeReader.git), we were able to capture the last two digits (port 80). Can you help us capture all four digits, including port 81?
I tried this git (git clone https://github.com/MrGreensWorkshop/RasPiPicoSDK-PicoBiosPostCodeReader.git) but i am getting below output: (not port80 or port81)
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
We need only port81 data followed by port80. can you please help us by providing the code sir.

[MaryJosephine123]

Hi,
Could you please help us to get only port80 and port81 data??