-
Notifications
You must be signed in to change notification settings - Fork 0
Old / abandoned NeoVGA VHDL source. Will not be maintained.
License
Mikejmoffitt/NeoVGA
Folders and files
Name | Name | Last commit message | Last commit date | |
---|---|---|---|---|
Repository files navigation
NeoVGA ====== Overview -------- This is the VHDL source of my old NeoVGA project, which samples Neo-Geo pixel data before the DAC, and produces a line-doubled 480p image. Features: * Selectable 240p or 480p output resolution * Selectable RGB or YUV colorspace output * Optional scanline overlay for odd lines when in 480p * Latency of ~70us, one scanline, which is ~3% of a frame * Optional sync-on-green output Hardware -------- This project targeted an Altera Cyclone II EP2CT144C6N FPGA, but should work on anything with enough block RAM. It uses no particularly special IO, though you should have a level translating buffer for the inputs, and use a dedicated clock pin if possible. The DAC was an Analog Devices ADV7123, a parallel 10-bit triple video DAC. Code quality and status ----------------------- I wrote this when I was a student, learning some VHDL for a class. I do not do much synthesis work now, but if I did, I would likely teach myself Verilog and go from there. This project works, and can maybe be useful to somebody. However, please be mindful that the code quality is likely fairly poor when compared to that of somebody with more experience. Do not use this as a reference for best practices. Possible Improvements --------------------- Looking back, a few things could be improved. * It would be nice to allow for the scanout to operate in a separate clock domain, optionally, so that some degree of width control could be realized. * The RGB2YUV should use proper arithmetic, instead of my solving for coefficients as sums of bit-twiddling logic, to allow for flexibiltity. * The RGB2YUV module should have an optional stage of delay for the luma output, as many monitors have a little delay on the chroma lines. * Symbol names across the board should be more consistent and readable. * The raster and blanking timings should be generalized, so that this is more reasily adapted to other systems with a readily available digital pixel bus.
About
Old / abandoned NeoVGA VHDL source. Will not be maintained.
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published