Make sure that we do not use unsupported features by NanoMips

clang/include/clang/Basic/DiagnosticCommonKinds.td

@@ -306,6 +306,8 @@ def err_opt_not_valid_without_opt : Error<
   "option '%0' cannot be specified without '%1'">;
 def err_opt_not_valid_on_target : Error<
   "option '%0' cannot be specified on this target">;
+def err_feature_not_valid_on_target : Error<
+  "feature '%0' cannot be specified on this target">;
 
 // Source manager
 def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;

clang/lib/Basic/Targets/Mips.cpp

@@ -309,7 +309,62 @@ bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
   // P32 ABI is only supported on NanoMIPS
   if (getTriple().isNanoMips() != (ABI == "p32")) {
     Diags.Report(diag::err_target_unsupported_abi_for_triple)
-      << ABI << getTriple().str();
+        << ABI << getTriple().str();
+    return false;
+  }
+
+  // Validate NanoMips target features.
+  if (getTriple().isNanoMips()) {
+    // NanoMips supports LE only.
+    if (BigEndian) {
+      Diags.Report(diag::err_opt_not_valid_on_target) << "-BE" << CPU;
+      return false;
+    }
+
+    // NanoMips supports soft float only.
+    if (FloatABI == HardFloat) {
+      Diags.Report(diag::err_target_unsupported_abi_for_triple)
+          << "hard-float" << getTriple().str();
+      return false;
+    }
+
+    // NanoMips supports p32 ABI only.
+    if (ABI != "p32") {
+      Diags.Report(diag::err_target_unsupported_abi_for_triple)
+          << ABI << getTriple().str();
+      return false;
+    }
+
+    // NanoMips does not support dsp.
+    if (DspRev != NoDSP) {
+      Diags.Report(diag::err_opt_not_valid_on_target) << "-mdsp/-mdspr2" << CPU;
+      return false;
+    }
+
+    // NanoMips does not support MSA.
+    if (HasMSA) {
+      Diags.Report(diag::err_opt_not_valid_on_target) << "-mmsa" << CPU;
+      return false;
+    }
+
+    // NanoMips does not support mips16.
+    if (IsMips16) {
+      Diags.Report(diag::err_opt_not_valid_on_target) << "-mips16" << CPU;
+      return false;
+    }
+
+    // NanoMips does not support micromips.
+    if (IsMicromips) {
+      Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU;
+      return false;
+    }
+
+    // NanoMips does not support indirect jump hazards.
+    if (UseIndirectJumpHazard) {
+      Diags.Report(diag::err_feature_not_valid_on_target)
+          << "use-indirect-jump-hazard" << CPU;
+      return false;
+    }
   }
 
   return true;

clang/lib/Basic/Targets/Mips.h

@@ -67,17 +67,18 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
         IsSingleFloat(false), IsNoABICalls(false), CanUseBSDABICalls(false),
         FloatABI(HardFloat), DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
         UseIndirectJumpHazard(false), FPMode(FPXX) {
-
     TheCXXABI.set(TargetCXXABI::GenericMIPS);
 
-    if (Triple.isMIPS32())
+    if (Triple.isMIPS32()) {
       setABI("o32");
-    else if (Triple.isNanoMips())
+    } else if (Triple.isNanoMips()) {
       setABI("p32");
-    else if (Triple.getEnvironment() == llvm::Triple::GNUABIN32)
+      IsNanoMips = true;
+    } else if (Triple.getEnvironment() == llvm::Triple::GNUABIN32) {
       setABI("n32");
-    else
+    } else {
       setABI("n64");
+    }
 
     CPU = ABI == "p32" ? "nanomips" : ABI == "o32" ? "mips32r2" : "mips64r2";
 
@@ -338,10 +339,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
     IsNan2008 = isIEEE754_2008Default();
     IsAbs2008 = isIEEE754_2008Default();
     IsSingleFloat = false;
-    if (IsNanoMips)
-      FloatABI = SoftFloat;
-    else
-      FloatABI = HardFloat;
+    FloatABI = IsNanoMips ? SoftFloat : HardFloat;
     DspRev = NoDSP;
     FPMode = isFP64Default() ? FP64 : FPXX;
     for (const auto &Feature : Features) {

clang/lib/Driver/ToolChains/Clang.cpp

@@ -2001,6 +2001,97 @@ void Clang::AddMIPSTargetArgs(const ArgList &Args,
       }
     }
   }
+
+  // NanoMips does not support SmallData, so force it to 0, since the default is
+  // 8 for Mips architectures.
+  if (Triple.isNanoMips()) {
+    CmdArgs.push_back("-msmall-data-limit");
+    CmdArgs.push_back("0");
+
+    CmdArgs.push_back("-mllvm");
+    CmdArgs.push_back("-mips-ssection-threshold=0");
+  }
+
+  // In the case of NanoMips, warn about using all MIPS legacy options that are
+  // supported by LLVM.
+  if (Triple.isNanoMips()) {
+    // -mabicalls option.
+    if (auto *A = Args.getLastArg(options::OPT_mabicalls,
+                                  options::OPT_mno_abicalls)) {
+      if (A->getOption().matches(options::OPT_mabicalls)) {
+        D.Diag(diag::err_opt_not_valid_on_target)
+            << A->getOption().getName() << CPUName;
+      }
+    }
+
+    // -mbranch-likely option.
+    if (auto *A = Args.getLastArg(options::OPT_mbranch_likely,
+                                  options::OPT_mno_branch_likely)) {
+      if (A->getOption().matches(options::OPT_mbranch_likely)) {
+        D.Diag(diag::err_opt_not_valid_on_target)
+            << A->getOption().getName() << CPUName;
+      }
+    }
+
+    // -mfp32, mfpxx and mfp64 options.
+    if (auto *A = Args.getLastArg(options::OPT_mfp32, options::OPT_mfpxx,
+                                  options::OPT_mfp64)) {
+      D.Diag(diag::err_opt_not_valid_on_target)
+          << A->getOption().getName() << CPUName;
+    }
+
+    // -mabs= option.
+    if (auto *A = Args.getLastArg(options::OPT_mabs_EQ)) {
+      D.Diag(diag::err_opt_not_valid_on_target)
+          << A->getOption().getName() << CPUName;
+    }
+
+    // -mnan= option.
+    if (auto *A = Args.getLastArg(options::OPT_mnan_EQ)) {
+      D.Diag(diag::err_opt_not_valid_on_target)
+          << A->getOption().getName() << CPUName;
+    }
+
+    // -mips16 option.
+    if (auto *A =
+            Args.getLastArg(options::OPT_mips16, options::OPT_mno_mips16)) {
+      D.Diag(diag::err_opt_not_valid_on_target)
+          << A->getOption().getName() << CPUName;
+    }
+
+    // -mmicromips option.
+    if (auto *A = Args.getLastArg(options::OPT_mmicromips,
+                                  options::OPT_mno_micromips)) {
+      D.Diag(diag::err_opt_not_valid_on_target)
+          << A->getOption().getName() << CPUName;
+    }
+
+    // -mrelax-pic-calls option.
+    if (auto *A = Args.getLastArg(options::OPT_mrelax_pic_calls,
+                                  options::OPT_mno_relax_pic_calls)) {
+      D.Diag(diag::err_opt_not_valid_on_target)
+          << A->getOption().getName() << CPUName;
+    }
+
+    // -mxgot option.
+    if (auto *A = Args.getLastArg(options::OPT_mxgot, options::OPT_mno_xgot)) {
+      D.Diag(diag::err_opt_not_valid_on_target)
+          << A->getOption().getName() << CPUName;
+    }
+
+    // -modd-spreg option.
+    if (auto *A = Args.getLastArg(options::OPT_modd_spreg,
+                                  options::OPT_mno_odd_spreg)) {
+      D.Diag(diag::err_opt_not_valid_on_target)
+          << A->getOption().getName() << CPUName;
+    }
+
+    // -mcompact-branches= option.
+    if (auto *A = Args.getLastArg(options::OPT_mcompact_branches_EQ)) {
+      D.Diag(diag::err_opt_not_valid_on_target)
+          << A->getOption().getName() << CPUName;
+    }
+  }
 }
 
 void Clang::AddPPCTargetArgs(const ArgList &Args,

llvm/lib/Target/Mips/MipsSubtarget.h

@@ -335,7 +335,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
   bool useIndirectJumpsHazard() const {
     return UseIndirectJumpsHazard && hasMips32r2();
   }
-  bool useSmallSection() const { return UseSmallSection; }
+  bool useSmallSection() const { return UseSmallSection && !hasNanoMips(); }
 
   bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
 

llvm/lib/Target/Mips/MipsTargetObjectFile.cpp

@@ -100,6 +100,9 @@ IsGlobalInSmallSectionImpl(const GlobalObject *GO,
   if (!Subtarget.useSmallSection())
     return false;
 
+  assert(!Subtarget.hasNanoMips() &&
+         "NanoMips does not support small data section");
+
   // Only global variables, not functions.
   const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GO);
   if (!GVA)

llvm/test/CodeGen/Mips/nanomips/globaladdr.ll

@@ -7,7 +7,7 @@ define i32 @load_global_val() {
 ; CHECK-LABEL: load_global_val
 ; CHECK: lwpc $a0, single
 ; CHECK-GP-LABEL: load_global_val
-; CHECK-GP: lw $a0, %gp_rel(single)($gp)
+; CHECK-GP: lwpc $a0, single
   %r = load i32, i32* @single
   ret i32 %r
 }
@@ -16,7 +16,7 @@ define i32* @load_global_addr() {
 ; CHECK-LABEL: load_global_addr
 ; CHECK: la $a0, single
 ; CHECK-GP-LABEL: load_global_addr
-; CHECK-GP: addiu $a0, $gp, %gp_rel(single)
+; CHECK-GP: la $a0, single
   ret i32* @single
 }