[2.0.x] fix possible race condition

[GMagician]

Fix some commits done in #11900

[thinkyhead]

What makes you think this fixes a race condition?

[GMagician]

If reset variable order is not correct you may reset first live but in meantime a temp isr may be executed and live may be updated (count is 1) and after interrupt you reset count (already 0 because of interrupt).
In this case if you are unlucky livew is not reset at all

[thinkyhead]

Are you sure that the order is reversed by the existing syntax? I would expect them to be set to zero in the given order, first endstop_poll_count and then validated_live_state. Does C++ formally define this?

[thinkyhead]

Apparently it does. I'd've expected the standard to be less formal and simply make it equivalent, but in strict mode the compiler will be more literal about it.

[GMagician]

Not sure but I think is compiler dependent (depending on optimizations)

[GMagician]

Are you sure that the order is reversed by the existing syntax? I would expect them to be set to zero in the given order, first endstop_poll_count and then validated_live_state. Does C++ formally define this?

From my memory with x86 C I remember that order is from right to left but not sure if optimizations don't change (don't know if this is strictly ruled)

[GMagician]

I found this....
https://stackoverflow.com/questions/19353686/multiple-assignment-in-one-line

[thinkyhead]

Yep, that's the same post I found before posting "Apparently it does…"