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A project from the FPGA-Based Design Methodology for Advanced Digital Systems course

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Basic Introduction

This project is part of the FPGA-Based Design Methodology for Advanced Digital Systems course, offered by the Department of Electronic Engineering at Tsinghua University in China.

In this project, I aim to implement a basic simulation of the Efficient Inference Engine (EIE), as described in the paper "EIE: Efficient Inference Engine on Compressed Deep Neural Network" (S. Han et al., ISCA 2016) This implementation does not involve hardware; it consists solely of Verilog and Python code.

The primary objective of this project is to leverage the inherent sparsity in Convolutional Neural Networks (CNNs) to accelerate computation and reduce memory usage.

For more detailed information, please refer to the Readme.pdf, which also served as a project report for the course. Apologies for only providing the Chinese version at the moment. The file arrangement can be found at the end of the PDF.

Disclaimer

This project is a reproduction of the concepts and methods presented in the paper "EIE: Efficient Inference Engine on Compressed Deep Neural Network" (S. Han et al., ISCA 2016). It is part of the FPGA-Based Design Methodology for Advanced Digital Systems course at Tsinghua University. The implementation is intended for educational purposes only and is not an original work.

The code and materials provided here aim to demonstrate an understanding of the ideas discussed in the paper. While we have made every effort to ensure correctness, there may still be errors or omissions. Users are responsible for verifying the results and using this code at their own risk.

Important Notice:
Students enrolled in the same course are strictly prohibited from using this code in any form without prior permission. Unauthorized use of this project, whether partially or entirely, for coursework, assignments, or evaluations violates academic integrity policies and is not allowed. Completing assignments independently is essential for developing practical skills and gaining a deeper understanding, which will greatly benefit students in the long run.

This project is not intended for commercial or production use. By using this repository, you acknowledge and accept the terms outlined in this disclaimer.

If having any questions, feel free to contact me.

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A project from the FPGA-Based Design Methodology for Advanced Digital Systems course

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