🌱 CompSci Junior @SUSTech supervised by HAO Qi
✨ Interested in applications of maching learning in autonomous systems
📧 Reach me via [email protected]
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RISC-V-CPU
RISC-V-CPU PublicRISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100
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SUSSYCourses
SUSSYCourses PublicSUSSYCourses: Role-based OpenCourseWare Web App in Vue.js + Spring Boot - SUSTech project of CS309: Object-oriented Analysis and Design in Fall 2024 - Score: 100/100
Vue 1
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Shenzhen-Metro
Shenzhen-Metro PublicShenzhen Metro: Metro Management System - Database and API Design Projects - SUSTech projects of CS307: Principles of Database System in Spring 2024 - Scores: 95/100 for Project 1 and 102/100 for P…
Java 1
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Digital-Piano
Digital-Piano PublicDigital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
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Jungle-Chess
Jungle-Chess PublicJungle: Chess Game Engine - Implementation of Minimax, Alpha-Beta Pruning, Move Ordering, and Quiescence Search - SUSTech project of course CS109: Introduction to Programming in Spring 2023 - Score…
Java 3
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