THEORY

In this project we will incorporate a standard cell design based on skywater PDKs and plug it in a design Picorv32, a RISC V CPU core. It implements the RISC-V instruction set architecture (ISA).

A brief description of the Picorv32:

The die is the part of a wafer of Silicon or any other material, but in semiconductor industry its Silicon. The core or the are within which chips are contained are compartmented within the core. There are input and output contacts, clocks on the IO pad that surround the core area and is a no logic zone.

The IPs are the intellectual property and they are logic blocks that took some intelligence to be built.

Final project showing our chip as encircled on the PCB after being manufactured and packaged by the foundary:

Pictorial representation of the processes and resources required for Digital ASIC Design

RTL designs: Basic netlist or a connection of network of the logics. There are several open sources that cater to development of a RTL design: Eg. github. PDKs : Process design kits, they contain files and resources pertaining to necessary information required for development of an IC. EDA Tools: They are design automation tool that nculcate the whole physical design flow processes , namely : QFlow, Openroad, Openlane.

Basic ASIC Flow Architecture:

Steps that occur in Physical design:

1. Synthesis: It is the step involving RTL Synthesis
2. Floorplanning: It involves placing the macro as well as the rows used for placement and routing and defines input and output ports.
3. Placement : Placement of component cells in the design.
4. CTS (Clock Tree Synthesis) : Clock network distribution.
5. Routing : Defining network routes.
6. Tapeout : Define final GDSII layout file from routing def file.
7. Signoff : Final step involving DRC, LVS ,Antenna Checks and ERC.

The tools that we utilized in our project are :

1. Yosys Synthesis suite.
2. Openlane RTL2GDS digital design suite.
3. NGSpice for characterization.
4. MAGIC for layout and floorplanning.
5. OpenSTA for static timing analysis.

The Openlane flow in interactive mode is generally is as follows:

1. prep -design -tag -init_design_config -overwrite
2. run_synthesis
3. run_floorplan
4. run_placement
5. run_cts
6. run_routing
7. run_magic
8. run_magic_spice_export
9. run_magic_drc
10. run_netgen
11. run_magic_antenna_clock

DAY 1

1. Openlane loaded and design preparation is initiated.

2)Synthesis performed in openlane

3. Number of cell synthesised is highlighted in the picture below:

4. Number of D flip flops is highlighted below: Flop ratio = Number of D flip flop/ Number of Cells = 1613/14876= 0.1084296854

5. Configuration README.md files showing all the parameters.

   DAY 2

6. Floorplan.tcl shows the default parameters.

7. Floorplanning run successfully

8. Core utilization is a representation of how much core area is utilized. In this case it's 35. The lesser the core utilization, the better it is for us.

   

9. The die are as highlighted in the def files is 660685 X 671405 = 443587212425 sq units

10. Running floorplan in magic:

11. Zoomed in floorplan showing grid cell and pin cell:

12. Executing placement in openlane flow:

13. Placement observed using magic. All the standard cells are within column and are legally placed.

14. Pins are equidistant now and standard cells lie in the left bottom corner.

DAY 3

1. Upon changing IOmode variable from floorplan.tcl of configuration in openlane and running floorplanning, it is found that pin configuration has changed.

2. Spice deck creation for CMOS inverter. Sky130A.tech file copied:

3. Load an inverter standard cell layout through magic.

4. tkcon console to interact with the layout.

5. Removal of layer shows DRC errors, as highlighted by white patches in the picture.

6. Extrack the layout design and use it for ngspice along with it all the parasitic capacitances and resistances will be extracted as well.

7. Check if the new file is created in the vsdstdcelldesign.

8. The spice program initially looks like :

9. Edit the spice program to change the scale as 0.01um, include the nmos and pmos lib files, make all the changes and perform transient analysis.

10. The following plot is obtained :

11. Cell Characterization done on the basis of data points obtained from the curve is :

12. Rise time = 3.901 e-9 – 3.522 e-9 = 0.379 ns

13. Fall time = 4.541 e-9 – 4.335 e-9 = 0.106 ns

14. Cell rise delay = 4.500 e-9 – 3.731 e-9 = 0.769 ns

15. Cell fall delay = 4.438 e-10 – 3.50 e-10 = 0.093 ns

16. Download and install drc_tests and run magic:

17. Load met3.mag file on magic to explore the DRC rules:

18. Rules pertaining to m3 mentioned on the website

19. cif see VIA2 is derived command and shows the mask cuts that will finally be available in GDSII. It hold to the DRC rules.

20. Rules pertaining to poly.lib on skywater website in the periphery section of the rules:

21. Poly.lib loaded on magic.

22. DRC rules pertaining to poly as defined a) Poly.9 giving error upon editing its drc rules in tech file in response to a DRC check. b) Similarly for poly.2 upon changing its drc rule in tech file, it is giving an error.

23. Lab to implement poly resistor spacing and diff and tap and seeing those error using drc why command in tkcon

24. Lab challenge exercise to describe DRC error as a geometrical construct. a) Geometric rules pertaining to nwell and their description in tech file: b) Observe nwell shrink, the are within is highlighted: c) Observe temporary layer, which shows the error

25. Lab to find missing or incomplete rule and fix them. Eg. n-well: a) Rules pertaining to n-well

26. Load n-well

27. Create a new DRC rule. Copy cifmaxwidth rule to nwell and change name to nwell_untapped.

28. Create templayer. Create n well that are tapped and leave all n well that are not tapped.

29. Wrap the rules in variant drc full as shown. Implying it is only checked for drc style full.

30. Check implementation of new DRC rule for tapped and untapped nwell:

    DAY 4

31. Load tracks.info to show track info from openlane directory

32. Tracks.info file containing all the tracks’ information, consisting of metal layers and the topmost two lines are horizontal and vertical origin and span

33. Create grid, which also useful for routing

34. Lab input and outputs lie at the intersection of horizontal and vertical lines

35. Width and length of std cell are odd multiples of x pitch and ypitch. Here they are 3 and 9.

36. To define a port write the following commands in console window after selecting them:

37. For output port Y:

port class output

port use signal

3. For Input port class input

port use signal

4. For VPWR

port class inout

port use power

5. For VGND

port class inout

port use ground

7. Saved file as sky130_vsdkashinv.mag

8. Lef file created

9. Lef file having pins that were converted from ports

10. Export lef file to picorv32a

11. Copying lef file and libraries to src folder

12. Synthesis initiated on openlane With the following steps: prep -design picorv32a -tag <tag_nam> -overwrite set lefs [glob $::env(DESIGN_DIR)/src/*.lef] add_lefs -src $lefs

    

    Now forgo the following steps: prep -design picorv32a -tag <tag_name> -overwrite

    set lefs [glob $::env(DESIGN_DIR)/src/*.lef]

    add_lefs -src $lefs

    set lefs [glob $::env(DESIGN_DIR)/src/*.lef]

    add_lefs -src $lefs

    echo $::env(SYNTH_STRATEGY)

    set ::env(SYNTH_STRATEGY) "DELAY 3"

    echo $::env(SYNTH_BUFFERING)

    echo $::env(SYNTH_SIZING)

    set ::env(SYNTH_SIZING) 1

    echo $::env(SYNTH_DRIVING_CELL)

13. Parameters optimised to minimise tns and wns value although with the tradeoff of gain in area

14. Now run the floorplan

15. On running floorplan we get the following errors Fix them using the following commands :

1. init_floorplan

2. place_io

3. tap_decap_or

   floorplan.def is created.

16. Run Placement

17. Load placement def file in magic

18. Expand to see the connectivity to the power and ground rails:

19. Our cell is in lef file pertaining to placement

20. Optimise parameters to reduce output load capacitances Although no buffer pins are present we experiment with pin replacement and output load. Replace pins of net _3697 from 2 to 1 Observe capacitance to be reduced:

    Create pre_sta.config that contains flow and addresses as well as link Create my_base.sdc file that contains the constraints, whose variables are read by sdc files: run openSTA outside of flow to get STA results We can explain the above report by probable mismatch in sdc file and config.tcl

21. Run CTS

    DAY 5

22. Generate PDN

23. Run routing

    Detailed routing, iterations are happening and memory is left Routing Completed

24. Post routing:

    Parasitic extraction SPEF file creation: For post routing analysis, the Verilog file we require to do it and we can use same sdc

Acknowledgements

Kunal Ghosh, Co-founder VSD Coporation Private Limited.

Nickson P Jose, Physical Design Engineer, Intel Corporation.

R. Timothy Edwards, Senior Vice President of Analog and Design, efabless Corporation.