#Author:
Jordi Jaspers
#Date of initial commit:
28/12/2018
#ARMv8_Pipeline
An Arm V8 processor with pipelining made via the instructions of the ARM-Edition book written by David A. Patterson & John L. Hennesey
#What I learned
- Advanced verilog & VHDL programming
- How parallel processing work instead of the regular sequential processing
- Workings of a processor (Also see Tamarac on my github)
- Understanding and importance of pipelining with error detection
#DISCLAIMER:
All the code that is copied or used from other sources will be mentioned in the reference section of this file.
#TODO list:
The pipelining processor is made out of 9 modules or 5 big parts and ofcourse a testfile.
==> Fetch, Decode, Execute, Data-Acces, Write-Back.
- RegisterFile --> done! (gebruikt van de single_cycle)
- ProgramCounter --> done! (is verwerkt in de pipelining zelf. geen apparte file meer.)
- SignExtend --> done! (gebruikt van de single_cycle)
- ALU --> done! (gebruikt van de single_cycle)
- ALUControl --> done! (gebruikt van de single_cycle)
- DataMemory --> done! (gebruikt van de single_cycle)
- InstructionMem --> done! (gebruikt van de single_cycle)
- Piplining --> done!
- Control --> done! (gebruikt van de single_cycle)
- Test file? --> done!
#References:
StackOverflow: (Bible for every coder)
https://www.StackOverflow.com/
Verilog fundamentals:
https://cseweb.ucsd.edu/classes/sp09/cse141L/Slides/01-Verilog1.pdf
LEGV8 16bit component example:
https://github.com/surajmehta95/LEGV8-Processor