Hardware-Modeling-using-Verilog

This repo contains the programming assignments and weekly quizzes of NPTEL course - Hardware Modeling using Verilog

Description of the programming assignments

1. Week 2 (w2) - Implement Half Adder and 2-bit full adder
2. Week 3 (w3) - Implement D-flipflop and 8bit shift register with it
3. Week 4 (w4) - a) 3-bit comparator using primitive construct b) 10-bit BCD encoder
4. Week 5 (w5) - FSMs for calling bell and timer
5. Week 6 (w6) - FSM for counter with separate datapath and controlpath
6. Week 7 (w7) - Implement 2-bit full adder and use it to implement an 8-bit pipelined adder