[DCP][Performance] Speed up direct symmetric-memory Output/LSE

[foraxe]

Draft: Speed up direct symmetric-memory DCP Output/LSE

Hi @GirasoleY,

This is a focused follow-up to vllm-project#48897. It keeps the same PyTorch
symmetric-memory allocation, peer-pointer exchange, sharded destination
buffers, parity slots, and DBO workspace ownership, while replacing the hot
Output/LSE operation with three Triton kernels.

Before this PR, vllm-project#48897 launches four kernels:

partial output + LSE
        |
        v
increment epoch
        |
        v
dispatch output + LSE ---- direct peer writes ----> symmetric receive buffers
        |
        v
publish completion signals
        |
        v
wait + serial LSE weights + output combine --------> final output

The kernel organization was first developed for vllm-project#50009's generic VMM
Shared-DCP path; this follow-up adapts it to vllm-project#48897's symmetric-memory peer
pointers so the allocation and ownership model stay unchanged.

This PR reduces the operation to three kernels:

partial output + LSE
        |
        v
tiled Triton publish ------- direct peer writes ----> symmetric receive buffers
        |
        v
advance epoch + publish system-release signals
        |
        v
wait + vectorized LSE/output combine --------------> persistent final output

The producer writes each destination shard directly to that peer's symmetric
buffer. After a system-scope release signal, each consumer waits with
system-scope acquire semantics and computes the stable LSE-weighted output
directly into a persistent final buffer. This also removes the dedicated C++
extension introduced for this operation.

Why

The original combine kernel computes LSE weights serially on thread 0 and then
synchronizes the CTA before combining output. The new consumer vectorizes the
four-rank LSE reduction and output combine, while the tiled publisher preserves
large-row bandwidth.

Performance

Measured on 4x GB200 at fixed 1800 MHz SM clocks, DCP4, 64 total heads,
16 heads/rank, head dimension 512, BF16 output and FP32 LSE. Timings use CUDA
graphs, changing input before every sample, 50 warmups, 500 replays/sample,
7 samples/process, and three independent processes per arm.

Rows	Exact vllm-project#48897	This PR	Change
1	15.765 us	10.869 us	31.05% faster
8	16.417 us	11.625 us	29.19% faster
32	18.417 us	16.411 us	10.89% faster
64	21.606 us	21.776 us	0.79% slower
128	32.869 us	32.982 us	0.34% slower

At rows 32, the three paired wins were 10.84%, 11.03%, and 10.80%, and the
candidate process CV was 0.006%. The implementation is intentionally single
path: rows 64-128 are reported as near-parity rather than routed to a second
kernel after selection.

The matched GLM-5.2 c32 serving guardrail was neutral within run-to-run
variance: three-process mean TPOT improved 0.16% and throughput improved 0.12%,
while TTFT was unchanged. This PR does not claim an end-to-end serving speedup.

Metric	Exact vllm-project#48897 mean	This PR mean	Change	Exact CV	This PR CV
TPOT	47.209 ms	47.133 ms	0.16% better	3.74%	3.80%
Output throughput	511.946 tok/s	512.580 tok/s	0.12% better	3.03%	3.07%
p99 ITL	260.951 ms	262.830 ms	0.72% worse	10.65%	10.59%
TTFT	1914.807 ms	1915.107 ms	0.02% worse	1.18%	1.13%

Correctness

• DCP2 and DCP4
• FP16 and BF16 output
• base-e and base-2 LSE
• contiguous and padded noncontiguous inputs
• both DBO ubatch slots
• changing-input CUDA-graph replay in interleaved ubatch order

Result: 8 passed.

No runtime fallback is added. Unsupported selected-path geometry, dtype,
device, or capacity fails closed.

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