Change circuit translation to tuple the state instead of adding it to a record type

intTests/test_comp_bisim/build.sh

@@ -0,0 +1,10 @@
+#!/bin/bash
+
+ghdl analyze vhdl/add10.vhd
+yosys -m ghdl -s yosys/add10.ys
+
+ghdl analyze vhdl/pow4.vhd
+yosys -m ghdl -s yosys/pow4.ys
+
+ghdl analyze vhdl/comp.vhd
+yosys -m ghdl -s yosys/comp.ys

intTests/test_comp_bisim/clean.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+
+rm -rf *.cf
+rm -rf *.json