w4_abc_{aiger,verilog}: Handle variable-less properties correctly
#1943
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Previously, any proofs involving the `w4_abc_aiger` (a.k.a., `abc`) or `w4_abc_verilog` proof scripts would succeed if they did not involve any variables, even false properties (e.g., `False`). This happened for a very silly reason: the counterexamples that the `abc` would generate contained a blank output (since there are no variables to describe), and SAW was misinterpreting this as a successful proof. Oops! With this patch, SAW now properly distinguishes between an successful proof (in which case no counterexample file will be generated) and a unsuccessful proof involving no variables (in which case a blank counterexample file will be generated). This is admittedly a bit fiddly, as it requires making some assumptions about the format of the counterexample files that `abc` produces. Nevertheless, this does work on all the examples that I have tried. Fixes #1938.
qsctr
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Sep 20, 2023
RyanGlScott
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PR: ready to merge
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Previously, any proofs involving the
w4_abc_aiger(a.k.a.,abc) orw4_abc_verilogproof scripts would succeed if they did not involve any variables, even false properties (e.g.,False). This happened for a very silly reason: the counterexamples that theabcwould generate contained a blank output (since there are no variables to describe), and SAW was misinterpreting this as a successful proof. Oops!With this patch, SAW now properly distinguishes between an successful proof (in which case no counterexample file will be generated) and a unsuccessful proof involving no variables (in which case a blank counterexample file will be generated). This is admittedly a bit fiddly, as it requires making some assumptions about the format of the counterexample files that
abcproduces. Nevertheless, this does work on all the examples that I have tried.Fixes #1938.