Skip to content

Commit

Permalink
Merge pull request #317 from zandrey/5.4-2.3.x-imx
Browse files Browse the repository at this point in the history
Update 5.4-2.3.x-imx to NXP [rel_imx_5.4.70_2.3.2] tag
  • Loading branch information
otavio authored Apr 27, 2021
2 parents e679197 + cffe4fb commit f5b1a0c
Show file tree
Hide file tree
Showing 73 changed files with 2,196 additions and 434 deletions.
11 changes: 11 additions & 0 deletions Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,9 @@ Optional properties:
The regulator will be enabled when initializing the PCIe host and
disabled either as part of the init process or when shutting down the
host.
- vph-supply: Should specify the regulator in charge of VPH one of the three
PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage
supplies. Might be used to distinguish different HW board designs.
- ext_osc: use the external oscillator as ref clock( 1: external OSC is
used, 0 internal PLL is used).
- hard_wired: the PCIe port is hard wired to the EP device(0: one slot
Expand All @@ -60,6 +63,9 @@ Optional properties:
- interrupt-names: Optional include the following entries:
- "dma": The interrupt that is asserted when an DMA interrupter
is received
- l1ss-disabled: Force to disable L1SS or not. If present then the L1
substate would be force disabled although it might be supported by the
chip.

Additional required properties for imx6sx-pcie:
- clock names: Must include the following additional entries:
Expand All @@ -83,6 +89,11 @@ Additional required properties for imx8mq-pcie:
- clock-names: Must include the following additional entries:
- "pcie_aux"

Additional required properties to enable L1sub for imx8mq-pcie, imx8mm-pcie
and imx8mp-pcie:
- reset-names: Must contain the following entries:
- "clkreq"

Additional required properties for imx8 pcie:
- hsio-cfg: hsio configration mode when the pcie node is supported.
mode 1: pciea 2 lanes and one sata ahci port.
Expand Down
4 changes: 3 additions & 1 deletion arch/arm64/boot/dts/freescale/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.d
imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-ab2.dtb imx8mp-evk-sof-wm8960.dtb \
imx8mp-evk-dsp.dtb imx8mp-evk-ov2775.dtb imx8mp-evk-basler.dtb imx8mp-evk-pcie-ep.dtb \
imx8mp-evk-spdif-lb.dtb imx8mp-evk-dsp-lpa.dtb imx8mp-evk-ov2775-ov5640.dtb \
imx8mp-evk-basler-ov5640.dtb imx8mp-evk-dual-ov2775.dtb
imx8mp-evk-basler-ov5640.dtb imx8mp-evk-dual-ov2775.dtb \
imx8mp-evk-basler-ov2775.dtb imx8mp-evk-dual-basler.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \
imx8mq-evk-usdhc2-m2.dtb imx8mq-evk-pcie-ep.dtb
Expand All @@ -97,6 +98,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \
imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \
imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \
imx8qm-mek-usdhc3-m2.dtb imx8qm-mek-usd-wifi.dtb \
imx8qm-mek-dp.dtb \
imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \
imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \
imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \
Expand Down
5 changes: 5 additions & 0 deletions arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
Original file line number Diff line number Diff line change
Expand Up @@ -343,20 +343,23 @@
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd IMX_SC_R_BOARD_R1>;
};

pca6416_2: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd IMX_SC_R_BOARD_R2>;
};

pca9548_1: pca9548@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
power-domains = <&pd IMX_SC_R_BOARD_R0>;

i2c@0 {
#address-cells = <1>;
Expand Down Expand Up @@ -467,13 +470,15 @@
#gpio-cells = <2>;
interrupt-parent = <&lsio_gpio2>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
power-domains = <&pd IMX_SC_R_BOARD_R4>;
};

pca9548_2: pca9548@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
power-domains = <&pd IMX_SC_R_BOARD_R3>;

i2c@0 {
#address-cells = <1>;
Expand Down
15 changes: 15 additions & 0 deletions arch/arm64/boot/dts/freescale/imx8mm-evk.dts
Original file line number Diff line number Diff line change
Expand Up @@ -230,7 +230,15 @@
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <100000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_250M>;
ext_osc = <1>;
l1ss-disabled;
status = "okay";
};

Expand All @@ -242,6 +250,13 @@
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <100000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_250M>;
ext_osc = <1>;
status = "disabled";
};
Expand Down
132 changes: 132 additions & 0 deletions arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts
Original file line number Diff line number Diff line change
@@ -0,0 +1,132 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020-2021 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include "imx8mp-evk.dts"

&iomuxc {
pinctrl_csi1_pwn: csi1_pwn_grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19
>;
};

pinctrl_csi1_rst: csi1_rst_grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19
>;
};
};

&i2c2 {
/delete-node/ov5640_mipi@3c;

basler_camera@36 {
compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam";
reg = <0x36>;
csi_id = <0x00>;
status = "okay";

port {
basler_ep_0: endpoint {
data-lanes = <1 2 3 4>;
clock-lanes = <0>;
link-frequencies = /bits/ 64 <750000000>;

max-lane-frequency = /bits/ 64 <750000000>;
max-pixel-frequency = /bits/ 64 <266000000>;
max-data-rate = /bits/ 64 <0>;

remote-endpoint = <&mipi_csi0_ep>;
};
};
};
};

&i2c3 {
/delete-node/ov5640_mipi@3c;

ov2775_1: ov2775_mipi@36 {
compatible = "ovti,ov2775";
reg = <0x36>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>;
pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
csi_id = <1>;
mclk = <24000000>;
mclk_source = <0>;
status = "okay";

port {
ov2775_mipi_1_ep: endpoint {
data-lanes = <1 2 3 4>;
clock-lanes = <0>;
max-pixel-frequency = /bits/ 64 <266000000>;

remote-endpoint = <&mipi_csi1_ep>;
};
};
};

};

&mipi_csi_0 {
status = "okay";

port@0 {
mipi_csi0_ep: endpoint {
remote-endpoint = <&basler_ep_0>;
data-lanes = <4>;
csis-hs-settle = <16>;
};
};
};

&mipi_csi_1 {
status = "okay";

port@1 {
mipi_csi1_ep: endpoint {
remote-endpoint = <&ov2775_mipi_1_ep>;
data-lanes = <4>;
csis-hs-settle = <16>;
};
};
};

&isi_0 {
status = "disabled";
};

&isi_1 {
status = "disabled";
};

&isp_0 {
status = "okay";
};

&isp_1 {
status = "okay";
};

&dewarp {
status = "okay";
};
7 changes: 6 additions & 1 deletion arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,12 @@
basler_ep_0: endpoint {
data-lanes = <1 2 3 4>;
clock-lanes = <0>;
link-frequencies = /bits/ 64 <248000000>;
link-frequencies = /bits/ 64 <750000000>;

max-lane-frequency = /bits/ 64 <750000000>;
max-pixel-frequency = /bits/ 64 <500000000>;
max-data-rate = /bits/ 64 <0>;

remote-endpoint = <&mipi_csi0_ep>;
};
};
Expand Down
5 changes: 4 additions & 1 deletion arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,10 @@
basler_ep_0: endpoint {
data-lanes = <1 2 3 4>;
clock-lanes = <0>;
link-frequencies = /bits/ 64 <248000000>;
link-frequencies = /bits/ 64 <750000000>;
max-lane-frequency = /bits/ 64 <750000000>;
max-pixel-frequency = /bits/ 64 <500000000>;
max-data-rate = /bits/ 64 <0>;
remote-endpoint = <&mipi_csi0_ep>;
};
};
Expand Down
Loading

0 comments on commit f5b1a0c

Please sign in to comment.