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Card-absorbed DFlash speculation: Laguna XS 2.1 FP8 + vLLM 0.25.1 matrix - #651

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feat/laguna-dflash-cards
Jul 22, 2026
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Card-absorbed DFlash speculation: Laguna XS 2.1 FP8 + vLLM 0.25.1 matrix#651
ttupper92618 merged 4 commits into
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feat/laguna-dflash-cards

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What

Extends the card-driven vLLM speculative-decoding fields so a vendor-published speculation scheme is absorbed as a card declaration, with no engine code or vendor fork, and ships the first card using it.

  • runtime.vllm_spec_method widens from "mtp" to "mtp" | "dflash". New runtime.vllm_spec_draft_repo names a separately published speculator repo and maps to the --speculative-config "model" key. A card model validator enforces the pairing both ways: dflash without a draft repo, or a draft repo under mtp (whose drafter lives inside the target checkpoint), fails loudly at card load instead of opaquely at serve time.
  • New bundled card poolside--Laguna-XS-2.1-FP8: Poolside's 33.4B MoE coding/agentic model, official FP8 release (~35 GB, fits 48 GB-class GPUs), 262k declared context (capped to 32k at the placement stamp like every vllm placement), paired with the vendor-published Laguna-XS-2.1-DFlash-FP8 block-parallel drafter at the vendor-recommended depth 15 (block size 16). License verified: OpenMDW-1.1 (permissive). Tool calling declared off pending vllm runner: implement tool calling (tool dispatch currently raises) #638; thinking declared with the template's default-off toggle, matching the feat: the wowsers vLLM slate: Qwen3.6 + Gemma 4 QAT + Ornith cards, native-MTP speculation, vLLM 0.24 matrix #649 slate precedent.
  • Validated vLLM matrix bumps 0.24.0+cu129 to 0.25.1+cu129 in install.sh. Verified against upstream tags directly: the dflash method and the Laguna target architecture exist at v0.24.0, but the Laguna DFlash drafter (DFlashLagunaForCausalLM) landed upstream in Add Laguna XS.2.1 DFlash drafter support vllm-project/vllm#46853 (2026-07-03) and first shipped in v0.25.0; the cu129 variant wheel for 0.25.1 exists on wheels.vllm.ai. The variant-wheel/ninja/index-pin rationale is unchanged.

The draft repo resolves through vLLM's own Hugging Face cache at engine start (the target model still stages through the Skulk model store); staging the draft through the store as a pinned companion is a follow-up.

Why

Poolside's own README routes llama.cpp users to a custom vendor branch for DFlash support. The point of the card-driven speculative fields is that Skulk absorbs a new vendor scheme generically: vLLM serves the whole pairing natively, and the card records the method, depth, and drafter as declarative model truth.

Docs

architecture-reference.md (engine facts + installer matrix), speculative-decoding.md + vllm-engine.md (DFlash sections), CLAUDE.md vllm bullet.

Validation

  • uv run basedpyright: 0 errors. uv run ruff check: clean. nix fmt: no changes. uv run pytest: 2750 passed, 1 skipped.
  • New tests: dflash serve-arg emission shape, card-validator pairing rejections (all three inconsistency cases), bundled-card invariant note.
  • Pod validation on a fresh GPU box (install path on 0.25.1, existing shipped vllm cards regression, Laguna XS with and without speculation) is running next and results will be posted on this PR before any merge consideration.

🤖 Generated with Claude Code

Vendor speculation schemes should be a card declaration, not an engine
fork. Poolside publishes their Laguna models with a separate
block-parallel DFlash speculator and documents serving it through a
custom llama.cpp branch; vLLM 0.25.0+ serves both the Laguna
architecture and its DFlash drafter natively, so Skulk absorbs the whole
scheme through the existing card-driven speculative fields:

- vllm_spec_method widens to Literal["mtp", "dflash"]; new
  vllm_spec_draft_repo names a separate speculator repo, mapped to the
  --speculative-config "model" key. The card validator enforces the
  pairing both ways (dflash requires a draft repo; a draft repo under
  mtp contradicts its in-checkpoint drafter contract) so custom cards
  fail loudly at load rather than opaquely at serve time. The draft
  repo resolves through vLLM's own Hugging Face cache at engine start;
  staging drafts through the model store is a follow-up.
- New card poolside--Laguna-XS-2.1-FP8 (33.4B MoE, ~35 GB FP8, 262k
  context, OpenMDW-1.1 license) paired with the vendor-published
  Laguna-XS-2.1-DFlash-FP8 drafter at the vendor-recommended depth 15
  (block size 16). Tool calling off pending #638, thinking declared
  with the template's default-off toggle, matching the #649 slate
  precedent.
- Validated vLLM matrix bumps 0.24.0+cu129 -> 0.25.1+cu129 in
  install.sh: 0.25.1 is the floor for the DFlash drafter architectures
  (the dflash method itself predates it; laguna_dflash.py landed
  upstream 2026-07-03 in vllm-project/vllm#46853 and first shipped in
  v0.25.0). The cu129-variant-wheel/ninja/index-pin rationale is
  unchanged.

Docs: architecture-reference.md (engine facts + installer matrix),
speculative-decoding.md and vllm-engine.md (DFlash section), CLAUDE.md
vllm bullet. Tests: serve-arg emission for the dflash config shape,
card-validator pairing rejections, bundled-invariant note.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Copilot AI review requested due to automatic review settings July 22, 2026 07:35

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Pull request overview

Extends Skulk’s card-driven vLLM speculative-decoding configuration to support vendor-published “draft model” schemes (DFlash) as pure model-card declarations, and updates the validated vLLM installer matrix accordingly. This keeps engine code generic while enabling Laguna XS FP8 + DFlash via a bundled card.

Changes:

  • Expand model-card runtime schema to support vllm_spec_method = "dflash" plus vllm_spec_draft_repo, with load-time validation for consistent field pairing.
  • Wire the new draft-repo field through the vLLM runner’s --speculative-config emission and add targeted unit tests.
  • Add the first bundled Laguna XS 2.1 FP8 card using DFlash and update docs + install.sh to vLLM 0.25.1+cu129.

Reviewed changes

Copilot reviewed 11 out of 11 changed files in this pull request and generated 2 comments.

Show a summary per file
File Description
website/docs/vllm-engine.md Documents DFlash as a card-declared speculative scheme for vLLM.
website/docs/speculative-decoding.md Adds DFlash explanation and how the same card fields cover separate-drafter schemes.
website/docs/architecture-reference.md Updates installer vLLM matrix to 0.25.1+cu129 and documents dflash + draft repo behavior.
src/skulk/worker/runner/vllm/tests/test_vllm_runner.py Tests --speculative-config JSON emission for dflash including the model key.
src/skulk/worker/runner/vllm/runner.py Adds spec_draft_repo plumbing into vllm serve args.
src/skulk/shared/tests/test_model_cards.py Adds tests for runtime speculative-field pairing validation at card load time.
src/skulk/shared/tests/test_bundled_model_cards.py Notes pairing is enforced by the card model validator (parse-time failure).
src/skulk/shared/models/model_cards.py Extends runtime config schema (dflash, vllm_spec_draft_repo) and enforces pairing via model validator.
resources/inference_model_cards/poolside--Laguna-XS-2.1-FP8.toml New bundled Laguna XS 2.1 FP8 vLLM card using dflash + vendor draft repo.
install.sh Bumps --with-vllm install to vllm==0.25.1+cu129 and updates wheel index URL.
CLAUDE.md Updates vLLM matrix and documents dflash + vllm_spec_draft_repo mapping.

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Comment thread src/skulk/worker/runner/vllm/runner.py
Comment thread src/skulk/shared/models/model_cards.py

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Reviewed commit: c84f25c581

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Comment thread resources/inference_model_cards/poolside--Laguna-XS-2.1-FP8.toml
…ncy, deep-spec scheduler sizing)

Fresh A100-80GB pod validation of this branch surfaced three defects; all
fixed here, each proven by the same pod run that found it:

- install.sh paired vllm==0.25.1+cu129 with --torch-backend=cu128, a
  leftover from the 0.24.0 matrix. vllm 0.25.1 requires torchcodec>=0.14,
  which the cu128 torch index does not carry (tops out at 0.11.1+cu128),
  so resolution fails outright on a fresh box. Now cu129 (validated: the
  cu129 index carries torchcodec 0.15.0+cu129 and the install completes).
- install.sh --with-vllm was not idempotent: a re-run died at `uv venv`
  ("virtual environment already exists"). Now --allow-existing, matching
  the installer's documented idempotency.
- The runner could not bring up deep speculative depths: vLLM budgets
  draft slots out of --max-num-batched-tokens, and with its defaults
  (2048 batched tokens, 256 seqs) the scheduler budget goes non-positive
  at depth 9 ("max_num_scheduled_tokens is set to -1536" observed live
  with the depth-15 Laguna card). build_vllm_serve_args now emits
  --max-num-batched-tokens = max(8192, 2048 + 256 * (depth - 1)) for
  carded depths >= 8; shallow MTP depths keep vLLM's defaults untouched
  (the exact shape the #649 cards validated under). 8192 is the
  fresh-box-validated value for the Laguna depth-15 card.

Also recorded from the same run: measured DFlash numbers on the card
comment (1.35x single-stream on A100-80GB, acceptance length 3.44; the
A100 lacks native FP8 so the target runs Marlin W8A16, below the vendor's
1.7-2.6x on native-FP8 hardware) and the CUDA >= 12.8 toolchain
requirement for the DFlash NVRTC JIT (12.4 headers lack __nv_fp8_e8m0) in
install.sh, nvidia-cuda-nodes.md, vllm-engine.md, and
architecture-reference.md.

Validation: basedpyright 0 errors, ruff clean, nix fmt no changes,
pytest 2750 passed. New serve-arg tests cover the depth-15 sizing, the
no-flag shallow shape, and linear scaling past the floor.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
@ttupper92618

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Fresh-box pod validation (round 1) + fixes pushed

Validated on a fresh RunPod A100 80GB PCIe (~2.3 h, branch @ c84f25c). The run found three defects; all are fixed in e6be74d and each fix was proven by the same pod session that found it.

Defects found and fixed:

  1. install.sh paired vllm==0.25.1+cu129 with --torch-backend=cu128 (a 0.24.0-matrix leftover). vllm 0.25.1 requires torchcodec>=0.14, absent from the cu128 torch index, so a fresh install failed resolution. Fixed to cu129; install then completes.
  2. --with-vllm re-run was not idempotent (uv venv refuses an existing environment). Fixed with --allow-existing.
  3. The runner could not start deep speculative depths: vLLM's default scheduler budget (2048 batched tokens, 256 seqs) reserves draft slots per sequence and goes non-positive at depth 9 (observed live: "max_num_scheduled_tokens is set to -1536" with the depth-15 Laguna card). The runner now emits --max-num-batched-tokens = max(8192, 2048 + 256 * (depth - 1)) for carded depths >= 8; shallow MTP depths keep vLLM defaults untouched (the shape the feat: the wowsers vLLM slate: Qwen3.6 + Gemma 4 QAT + Ornith cards, native-MTP speculation, vLLM 0.24 matrix #649 cards validated under). Unit tests cover the depth-15 value, the shallow no-flag shape, and scaling past the floor.

What proved out (with the fixes/workarounds applied on-pod):

  • Spawned config exactly as designed: --speculative-config {"method": "dflash", "num_speculative_tokens": 15, "model": "poolside/Laguna-XS-2.1-DFlash-FP8"}; drafter fetched by vLLM at engine start in ~9 s.
  • Laguna XS 2.1 FP8 A/B, 3 runs each at temp 0: 1.35x single-stream (129 -> 174 tok/s median), mean acceptance length 3.44. Below the vendor's 1.7-2.6x because the A100 has no native FP8 (target runs Marlin W8A16); recorded on the card comment with that caveat.
  • Thinking default-off confirmed (no think markers on plain requests); output coherent.
  • Shipped-card regression on the bumped matrix: Qwen3.6-27B-FP8 brings up clean on 0.25.1 with its mtp spec config, decodes 97.3 tok/s (matching the card's documented 2.01x figure), acceptance length 2.70. gemma-4-12B w4a16 also brought up and completed cleanly.
  • One environment requirement documented rather than fixed in code: the DFlash speculator JIT-compiles through NVRTC and needs a CUDA >= 12.8 toolchain on the node (CUDA 12.4 headers lack __nv_fp8_e8m0). Now noted in install.sh, nvidia-cuda-nodes.md, vllm-engine.md, and architecture-reference.md.

Local gates on the fix commit: basedpyright 0 errors, ruff clean, nix fmt no changes, pytest 2750 passed.

The capability resolver has no laguna family branch, so the card's
thinking declaration resolved with thinking_format "none" in /v1/models
metadata while the model actually reasons behind <think> token delimiters.
The [reasoning] section states the model truth directly (token_delimited,
toggle-capable), matching the resolved shape of the Qwen3.6 vllm cards.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

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Comment thread resources/inference_model_cards/poolside--Laguna-XS-2.1-FP8.toml Outdated
The card's DFlash runtime JIT-compiles its speculator through NVRTC
(CUDA 12.8+), which has no ROCm path in vLLM 0.25.1. Advertising
vllm-rocm let placement route the instance to an AMD node that would
only fail at engine start; the card now declares vllm-cuda alone until
a ROCm validation pass proves the pairing (or cards it off per backend).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Copilot AI review requested due to automatic review settings July 22, 2026 10:20

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Pull request overview

Copilot reviewed 12 out of 12 changed files in this pull request and generated no new comments.

@ttupper92618
ttupper92618 merged commit 7a90bc3 into dev Jul 22, 2026
15 checks passed
@ttupper92618
ttupper92618 deleted the feat/laguna-dflash-cards branch July 22, 2026 13:30
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