[ROCm][MiniMax-M3] Skip contiguous copies on the AITER sparse-PA KV insert

[Fangzhou-Ai]

Purpose

Drop two .contiguous() calls in the MiniMax-M3 AITER sparse-PA KV insert. They were
pure overhead: two kernel launches per sparse layer, ~114 per decode step (~0.5 ms),
producing byte-identical data.

Why they are unnecessary

The k/v passed to reshape_and_cache are column slices of the fused qkv:

k = qkv[:, k_start:v_start].view(num_tokens, self.num_kv_heads, self.head_dim)

so their strides are (qkv.stride(0), head_dim, 1) — the token dim is strided, the inner
(num_heads, head_size) dims are contiguous.

reshape_and_cache takes key_stride/value_stride for exactly this case, and requires
only that the inner dims be contiguous:

// AITER  csrc/kernels/cache_kernels.cu   (i walks num_heads*head_size)
const int64_t src_key_idx = token_idx * key_stride + i;

// vLLM   csrc/libtorch_stable/cache_kernels.cu
key + token_idx * key_stride + head_idx * head_size + h_block * x;

Identical contract in both. The host wrapper reads key.stride(0)/value.stride(0) and
forwards them. The .view(...) that builds these tensors guarantees the inner dims are
contiguous, so the requirement is satisfied by construction — the output is bit-identical
with or without the copies.

Why it matters

MiniMax-M3 decode on MI355X is launch-bound, not bandwidth-bound: every small kernel
costs ~4.4 µs of in-graph dispatch regardless of how little work it does, and ~701
launches/step account for ~20% of the step. Removing 114 of them is worth more than the
memory traffic saved.

No knob, no fallback

The stride contract is structural rather than a property of a particular AITER build, and
all concurrencies benefit, so there is nothing to gate. An env-var escape hatch would only
add a dead branch that no test exercises.

Test Plan and Result

MiniMax-M3-MXFP4, MI355X, TP4, 8k/1k ISL/OSL, spec-none.

Base: vLLM at the Docker build commit with VLLM_ROCM_SHUFFLE_KV_CACHE_LAYOUT=1 and
nothing else — no online-quant overlay, no fusions, no tuned MoE config. The branch is the
only difference between the two arms. Sparse PA is required for the changed line to be
reached at all (_insert_aiter_sparse_pa_kv is called only under
if self.use_aiter_sparse_pa:), so it is in both arms.

MiniMax-M3-MXFP4, MI355X, TP4, 8k/1k ISL/OSL, spec-none, one sample per point.

conc	base	this PR		TPOT base -> PR
4	4,060	4,218	+3.9%	8.38 -> 8.05 ms
8	6,765	6,997	+3.4%	10.02 -> 9.66 ms
64	22,044	22,414	+1.7%	24.83 -> 24.42 ms
128	27,778	28,156	+1.4%	39.52 -> 38.97 ms

Positive at every concurrency and TPOT down at every concurrency, with the relative gain
shrinking monotonically as the step lengthens — the expected signature of removing a fixed
per-step cost. No concurrency regresses; the change removes work and adds none.

Accuracy: not re-measured for this isolated run. On the stacked configuration where this
was first tested, GSM8K 5-shot was 0.9439 / 0.9431 strided against 0.9454 / 0.9447
copying (n=1319, stderr ~0.006) — inside noise, as expected for a change that is
bit-identical by construction rather than approximate.

Lint: ruff check and ruff format --check (v0.14.0, as pinned in
.pre-commit-config.yaml) clean. pre-commit itself could not run — no pre_commit
module in the venv — so the hooks were run manually.

Duplicate check

gh pr list --repo vllm-project/vllm --state open --search over "reshape_and_cache
contiguous", "sparse_pa kv insert", "aiter reshape_and_cache", "strided kv insert" — no
overlapping PR. Nearest neighbours (vllm-project#45798, vllm-project#38313, vllm-project#44527) target MLA/DSv3.2 paths, not
the M3 sparse-PA insert.

Notes

AI assistance (Claude Code) was used for this change.

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