APB bus interface to fabric

[hnpatel81]

Hello,
We want to interface eFPGA fabric to RISC-V processor thorough AMBA AHB/APB bus. The target is that RISC-V processor should be able to read/write in RegFIle through this bus. Currently possible way is trough I/O_TOP to W_IO, but this approach will consume I/O pins and other routing resources. Is there any way to provide bus interface to RegFile without consuming routing resources and existing I/O pins ?

Regards,
Himanshu

[KelvinChung2000]

Option one would be to modify the RegFile Bel to have some external pin, which will directly go to the top interface of the fabric interface. You can directly implement the interface at the Bel or just have the pin out and then implement bus control outside the fabric.

Option two would be to modify the north/south terminal or the IO tile with extra wires. Those extra wires will be dedicated just for communicating with the RegFile using the bus interface.

[hnpatel81]

Thanks for your reply. As per your option one, We are trying to modify RegFile BEL for direct access to APB bus. Meanwhile can you please elaborate what is purpose of RAM_IO, does it provide RAM memory resource for data storage ?

[KelvinChung2000]

The default FABulous BRAM is not within the fabric but communicated through the RAM_IO.

[dishant1602]

Hi,

I am wondering that currently in the eFPGA_top.v, the BRAM is connected to RAM_IO via RAM2FAB and FAB2RAM. But there are globally no pins available using which I can provide inputs to RAM_IO.
So, are the inputs and outputs from RAM_IO propagating through W_IO and then to I_top and O_top?

[IAmMarcelJung]

Hi and thanks both of you for your interest in FABulous and all of your questions. I kindly want to remind you to create a new discussion for questions that are not directly related to the original topic. This helps keeping the discussion clean and will it make easier for people who may have the same questions in the future. Thanks in advance for you understanding :)