test/6800.c 6800 emulator's clock_count table is incorrect.

[zu2]

The number of 6800 instruction cycles listed in the 6800 emulator's clock_count table is incorrect.
This has been corrected from the MOTOROLA M6800 Microprocessor Applications Manual.

--- 6800.c.old 2024-08-19 05:47:45
+++ 6800.c 2024-08-19 05:51:41
@@ -228,14 +228,14 @@
{ 4, 3, 3, 3 }, /* BGT /
{ 4, 3, 3, 3 }, / BLE /
/ 0x30 */

• { 3, 3, 1, 1 }, /* TSX */
• { 3, 3, 1, 1 }, /* INS */

• { 4, 3, 1, 1 }, /* TSX */
• { 4, 3, 1, 1 }, /* INS /
  { 4, 4, 3, 3 }, / PULA /
  { 4, 4, 3, 3 }, / PULB */

• { 3, 3, 1, 1 }, /* DES */
• { 3, 3, 1, 1 }, /* TXS */
• { 3, 3, 4, 4 }, /* PSHA */
• { 3, 3, 4, 4 }, /* PSHB */

• { 4, 3, 1, 1 }, /* DES */
• { 4, 3, 1, 1 }, /* TXS */
• { 4, 3, 4, 4 }, /* PSHA */
• { 4, 3, 4, 4 }, /* PSHB /
  { 0, 5, 4, 4 }, / PULX /
  { 5, 5, 5, 5 }, / RTS /
  { 0, 3, 1, 1 }, / ABX /
  @@ -279,26 +279,9 @@
  { 2, 2, 1, 1 }, / HCF / T /
  { 2, 2, 1, 1 }, / CLRB /
  / 0x60 : indexed form */

• { 6, 6, 6, 6 }, /* NEG */

• { 7, 6, 6, 6 }, /* NEG /
  { 0, 0, 7, 7 }, / AIM /
  { 0, 0, 7, 7 }, / OIM */

• { 6, 6, 6, 6 }, /* COM */
• { 6, 6, 6, 6 }, /* LSR */
• { 0, 0, 6, 6 }, /* EIM */
• { 6, 6, 6, 6 }, /* ROR */
• { 6, 6, 6, 6 }, /* ASR */
• { 6, 6, 6, 6 }, /* ASL */
• { 6, 6, 6, 6 }, /* ROL */
• { 6, 6, 6, 6 }, /* DEC */
• { 0, 0, 5, 5 }, /* TIM */
• { 6, 6, 6, 6 }, /* INC */
• { 6, 6, 4, 4 }, /* TST */
• { 3, 3, 3, 3 }, /* JMP */
• { 6, 6, 5, 5 }, /* CLR */
• /* 70: extended form (immediate for AIM/OIM etc) */
• { 7, 6, 6, 6 }, /* NEG */
• { 0, 0, 6, 6 }, /* AIM */
• { 0, 0, 6, 6 }, /* OIM /
  { 7, 6, 6, 6 }, / COM /
  { 7, 6, 6, 6 }, / LSR /
  { 0, 0, 6, 6 }, / EIM /
  @@ -307,9 +290,26 @@
  { 7, 6, 6, 6 }, / ASL /
  { 7, 6, 6, 6 }, / ROL /
  { 7, 6, 6, 6 }, / DEC */
• { 0, 0, 4, 4 }, /* TIM */

• { 0, 0, 5, 5 }, /* TIM /
  { 7, 6, 6, 6 }, / INC /
  { 7, 6, 4, 4 }, / TST */
• { 4, 3, 3, 3 }, /* JMP */
• { 7, 6, 5, 5 }, /* CLR */
• /* 70: extended form (immediate for AIM/OIM etc) */
• { 6, 6, 6, 6 }, /* NEG */
• { 0, 0, 6, 6 }, /* AIM */
• { 0, 0, 6, 6 }, /* OIM */
• { 6, 6, 6, 6 }, /* COM */
• { 6, 6, 6, 6 }, /* LSR */
• { 0, 0, 6, 6 }, /* EIM */
• { 6, 6, 6, 6 }, /* ROR */
• { 6, 6, 6, 6 }, /* ASR */
• { 6, 6, 6, 6 }, /* ASL */
• { 6, 6, 6, 6 }, /* ROL */
• { 6, 6, 6, 6 }, /* DEC */
• { 0, 0, 4, 4 }, /* TIM */
• { 6, 6, 6, 6 }, /* INC */
• { 6, 6, 4, 4 }, /* TST /
  { 3, 3, 3, 3 }, / JMP /
  { 6, 6, 5, 5 }, / CLR /
  / 80: A ops, immed /
  @@ -325,7 +325,7 @@
  { 2, 2, 2, 2 }, / ADCA /
  { 2, 2, 2, 2 }, / ORAA /
  { 2, 2, 2, 2 }, / ADDA */

• { 4, 4, 3, 3 }, /* CPX */

• { 3, 4, 3, 3 }, /* CPX /
  { 8, 6, 5, 5 }, / BSR /
  { 3, 3, 3, 3 }, / LDS /
  { 3, 3, 3, 3 }, / STS immed (timing uncertain) 68HC11 only: XGDX /
  @@ -337,15 +337,15 @@
  { 3, 3, 3, 3 }, / ANDA /
  { 3, 3, 3, 3 }, / BITA /
  { 3, 3, 3, 3 }, / LDAA */

• { 3, 3, 3, 3 }, /* STAA */

• { 4, 3, 3, 3 }, /* STAA /
  { 3, 3, 3, 3 }, / EORA /
  { 3, 3, 3, 3 }, / ADCA /
  { 3, 3, 3, 3 }, / ORAA /
  { 3, 3, 3, 3 }, / ADDA */

• { 5, 5, 4, 4 }, /* CPX */

• { 4, 5, 4, 4 }, /* CPX /
  { 1, 5, 5, 5 }, / JSR (HCF on 6800)/
  { 4, 4, 4, 4 }, / LDS */

• { 4, 4, 4, 4 }, /* STS */

• { 5, 4, 4, 4 }, /* STS /
  / A0: A ops, indexed /
  { 5, 4, 4, 4 }, / SUBA /
  { 5, 4, 4, 4 }, / CMPA /
  @@ -354,15 +354,15 @@
  { 5, 4, 4, 4 }, / ANDA /
  { 5, 4, 4, 4 }, / BITA /
  { 5, 4, 4, 4 }, / LDAA */

• { 5, 4, 4, 4 }, /* STAA */

• { 6, 4, 4, 4 }, /* STAA /
  { 5, 4, 4, 4 }, / EORA /
  { 5, 4, 4, 4 }, / ADCA /
  { 5, 4, 4, 4 }, / ORAA /
  { 5, 4, 4, 4 }, / ADDA /
  { 6, 6, 5, 5 }, / CPX */

• { 9, 6, 5, 5 }, /* JSR */
• { 5, 5, 5, 5 }, /* LDS */
• { 5, 5, 5, 5 }, /* STS */

• { 8, 6, 5, 5 }, /* JSR */
• { 6, 5, 5, 5 }, /* LDS */
• { 7, 5, 5, 5 }, /* STS /
  / B0: A ops, extended /
  { 4, 4, 4, 4 }, / SUBA /
  { 4, 4, 4, 4 }, / CMPA /
  @@ -405,7 +405,7 @@
  { 3, 3, 3, 3 }, / ANDB /
  { 3, 3, 3, 3 }, / BITB /
  { 3, 3, 3, 3 }, / LDAB */

• { 3, 3, 3, 3 }, /* STAB */

• { 4, 3, 3, 3 }, /* STAB /
  { 3, 3, 3, 3 }, / EORB /
  { 3, 3, 3, 3 }, / ADCB /
  { 3, 3, 3, 3 }, / ORAB /
  @@ -413,7 +413,7 @@
  { 0, 4, 4, 4 }, / LDD /
  { 1, 4, 4, 4 }, / STD (HCF on 6800) /
  { 4, 4, 4, 4 }, / LDX */

• { 4, 4, 4, 4 }, /* STX */

• { 5, 4, 4, 4 }, /* STX /
  / E0: B ops, indexed /
  { 5, 4, 4, 4 }, / SUBB /
  { 5, 4, 4, 4 }, / CMPB /
  @@ -422,15 +422,15 @@
  { 5, 4, 4, 4 }, / ANDB /
  { 5, 4, 4, 4 }, / BITB /
  { 5, 4, 4, 4 }, / LDAB */

• { 5, 4, 4, 4 }, /* STAB */

• { 6, 4, 4, 4 }, /* STAB /
  { 5, 4, 4, 4 }, / EORB /
  { 5, 4, 4, 4 }, / ADCB /
  { 5, 4, 4, 4 }, / ORAB /
  { 5, 4, 4, 4 }, / ADDB /
  { 0, 5, 5, 5 }, / LDD /
  { 0, 5, 5, 5 }, / STD */

• { 5, 5, 5, 5 }, /* LDX */
• { 5, 5, 5, 5 }, /* STX */

• { 6, 5, 5, 5 }, /* LDX */
• { 7, 5, 5, 5 }, /* STX /
  / F0: B ops, extended /
  { 4, 4, 4, 4 }, / SUBB /
  { 4, 4, 4, 4 }, / CMPB /
  @@ -439,7 +439,7 @@
  { 4, 4, 4, 4 }, / ANDB /
  { 4, 4, 4, 4 }, / BITB /
  { 4, 4, 4, 4 }, / LDAB */

• { 4, 4, 4, 4 }, /* STAB */

• { 5, 4, 4, 4 }, /* STAB /
  { 4, 4, 4, 4 }, / EORB /
  { 4, 4, 4, 4 }, / ADCB /
  { 4, 4, 4, 4 }, / ORAB /
  @@ -447,7 +447,7 @@
  { 0, 5, 5, 5 }, / LDD /
  { 0, 5, 5, 5 }, / STD /
  { 5, 5, 5, 5 }, / LDX */

• { 5, 5, 5, 5 } /* STX */

• { 6, 5, 5, 5 } /* STX */
  };

/* By page 00/18/1A/CD */

[EtchedPixels]

Fixed in EmulatorKit

TODO: once emulatorkit has done a test cycle import it the changes here.