master contract draft

title: Implementing the Load Slice Core Microarchitecture in Chisel based on the BOOM RISC-V Processor

study program: Embedded Computing Systems (MSECS)

problem description: The Load Slice Core (LSC) Microarchitecture is a novel approach that tries to fit between the dominant in-order and out-of-order pipeline architectures. The LSC introduces a system of two queues, one for loads and the address generating instruction they depend upon and one for the other instructions. To sort instructions into queues it uses Iterative Backward Dependency Analysis, a technique that marks the register dependency chains of instructions. The goal of this thesis is to implement a LSC based on the Berkeley Out-of-Order Machine (BOOM), an open source RISC-V CPU implemented in Chisel, in order to evaluate both the LSC and the open source hardware development infrastructure surrounding BOOM.