Ddr2 ip update

if/vga_rtl_custom_rtl/vga_rtl_custom.xml

@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>user</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>vga_rtl_custom</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:extends spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="vga" spirit:version="1.0"/>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>

if/vga_rtl_custom_rtl/vga_rtl_custom_rtl.xml

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+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>user</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>vga_rtl_custom_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="user" spirit:library="user" spirit:name="vga_rtl_custom" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>CLK</spirit:logicalName>
+      <spirit:description>VGA Clock signal</spirit:description>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isClock>true</spirit:isClock>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>RED</spirit:logicalName>
+      <spirit:description>Red pixel data</spirit:description>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isData>true</spirit:isData>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+        </spirit:onMaster>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>GREEN</spirit:logicalName>
+      <spirit:description>Green data of the pixel</spirit:description>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isData>true</spirit:isData>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+        </spirit:onMaster>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>BLUE</spirit:logicalName>
+      <spirit:description>BLUE data of the pixel</spirit:description>
+      <spirit:wire>
+        <spirit:qualifier>
+          <spirit:isData>true</spirit:isData>
+        </spirit:qualifier>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+        </spirit:onMaster>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>HSYNC</spirit:logicalName>
+      <spirit:description>Horizantal sync signal</spirit:description>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>VSYNC</spirit:logicalName>
+      <spirit:description>Vertical sync signal</spirit:description>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>DPS</spirit:logicalName>
+      <spirit:description>Display scan signal</spirit:description>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>DE</spirit:logicalName>
+      <spirit:description>Display enable signal</spirit:description>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>

if/vga_rtl_custom_rtl/vga_rtl_custom_v1_0.sv

@@ -0,0 +1,95 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef vga_rtl_custom_v1_0
+`define vga_rtl_custom_v1_0
+
+package parameter_structs;
+
+  typedef struct packed {
+      bit    portEnabled;
+      integer    portWidth;
+  }portConfig;
+
+  typedef struct packed {
+    // <typeName> <LogicalName> = {<enablement>, <width>}
+    portConfig RED;
+    portConfig GREEN;
+    portConfig BLUE;
+  }vga_rtl_custom_v1_0_port_configuration;
+
+  parameter vga_rtl_custom_v1_0_port_configuration vga_rtl_custom_v1_0_default_port_configuration = '{RED:'{1, -1}, GREEN:'{1, -1}, BLUE:'{1, -1}};
+
+endpackage
+
+interface vga_rtl_custom_v1_0 #(parameter_structs::vga_rtl_custom_v1_0_port_configuration port_configuration)();
+  logic CLK;                                                       // VGA Clock signal
+  logic [port_configuration.RED.portWidth-1:0] RED;                // Red pixel data
+  logic [port_configuration.GREEN.portWidth-1:0] GREEN;            // Green data of the pixel
+  logic [port_configuration.BLUE.portWidth-1:0] BLUE;              // BLUE data of the pixel
+  logic HSYNC;                                                     // Horizantal sync signal
+  logic VSYNC;                                                     // Vertical sync signal
+  logic DPS;                                                       // Display scan signal
+  logic DE;                                                        // Display enable signal
+
+  modport MASTER (
+    output CLK, RED, GREEN, BLUE, HSYNC, VSYNC, DPS, DE
+    );
+
+  modport SLAVE (
+    output CLK, RED, GREEN, BLUE, HSYNC, VSYNC, DPS, DE
+    );
+
+  modport MONITOR (
+    input CLK, RED, GREEN, BLUE, HSYNC, VSYNC, DPS, DE
+    );
+
+endinterface // vga_rtl_custom_v1_0
+
+`endif