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dvi2rgb fixes for cadence #81

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dvi2rgb fixes for cadence #81

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34d8a44
Fix and update read mode
Oct 26, 2023
d03170c
Incisive doesn't support concatination on the instantion, do concat o…
Oct 26, 2023
c5bed9a
Incisive does not like unbounded addition, adding modulo to all cases…
Oct 26, 2023
dcd2bc4
Clean up OtherCh namibng to be more consistent
Oct 26, 2023
fa0492d
Merge branch 'develop' into dvd2rgb_fix
davekeeshan Dec 15, 2023
2cf76f8
Remove commented out lines
davekeeshan Dec 15, 2023
156cd56
Two more files that need to have modulo fixes that that they can work…
Apr 11, 2024
d35c3c7
Fix incorrect modulo number form 7 to 8
Apr 18, 2024
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4 changes: 2 additions & 2 deletions ip/dvi2rgb/src/ChannelBond.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
pWrA <= (pWrA + 1) mod kFIFO_Depth;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
Expand All @@ -115,7 +115,7 @@ begin
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
pRdA <= (pRdA + 1) mod kFIFO_Depth;
end if;
end if;
end process FIFO_RdA;
Expand Down
4 changes: 2 additions & 2 deletions ip/dvi2rgb/src/EEPROM_8b.vhd
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Expand Up @@ -87,7 +87,7 @@ constant kRAM_Width : integer := 8;
type eeprom_t is array (0 to 2**kAddrBits - 1) of std_logic_vector(kRAM_Width-1 downto 0);

impure function InitRamFromFile (ramfilename : in string) return eeprom_t is
file ramfile : text is in ramfilename;
file ramfile : text open read_mode is ramfilename;
variable ramfileline : line;
variable ram_name : eeprom_t;
variable bitvec : bit_vector(kRAM_Width-1 downto 0);
Expand Down Expand Up @@ -172,7 +172,7 @@ begin
if (sState = stRegAddress) then
sAddr <= to_integer(resize(unsigned(sI2C_DataIn), kAddrBits));
elsif (sState = stRead) then
sAddr <= sAddr + 1;
sAddr <= (sAddr + 1) mod (2**kAddrBits);
end if;
end if;
end if;
Expand Down
4 changes: 2 additions & 2 deletions ip/dvi2rgb/src/PhaseAlign.vhd
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Expand Up @@ -147,7 +147,7 @@ begin
if (pCtlTknRst = '1') then
pCtlTknCnt <= 0;
else
pCtlTknCnt <= pCtlTknCnt + 1;
pCtlTknCnt <= (pCtlTknCnt + 1) mod kCtlTknCount;
-- Overflow
if (pCtlTknCnt = kCtlTknCount - 1) then
pCtlTknOvf <= '1';
Expand Down Expand Up @@ -231,7 +231,7 @@ begin
if (pDelayWaitRst = '1') then
pDelayWaitCnt <= 0;
else
pDelayWaitCnt <= pDelayWaitCnt + 1;
pDelayWaitCnt <= (pDelayWaitCnt + 1) mod kDelayWaitEnd;
if (pDelayWaitCnt = kDelayWaitEnd - 1) then
pDelayWaitOvf <= '1';
else
Expand Down
4 changes: 2 additions & 2 deletions ip/dvi2rgb/src/TWI_SlaveCtl.vhd
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Expand Up @@ -179,10 +179,10 @@ DATABYTE_SHREG: process (SampleClk)
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
bitCount <= (bitCount - 1) mod 8;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
bitCount <= (bitCount - 1) mod 8;
end if;
end if;
end process;
Expand Down
12 changes: 10 additions & 2 deletions ip/dvi2rgb/src/dvi2rgb.vhd
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Expand Up @@ -167,6 +167,10 @@ signal dbg_pEyeSize : eyeSize_t;

signal pTrigOut, pTrigOutAck, rTrigOutAck, rTrigOut : std_logic;

type OtherCh_t is array (2 downto 0) of std_logic_vector(1 downto 0);
signal OtherChRdy : OtherCh_t;
signal OtherChVld : OtherCh_t;

begin

ResetActiveLow: if not kRstActiveHigh generate
Expand Down Expand Up @@ -226,6 +230,10 @@ LockedSync: entity work.ResetBridge

-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
OtherChRdy(iCh)(0) <= pRdy((iCh+1) mod 3);
OtherChRdy(iCh)(1) <= pRdy((iCh+2) mod 3);
OtherChVld(iCh)(0) <= pVld((iCh+1) mod 3);
OtherChVld(iCh)(1) <= pVld((iCh+2) mod 3);
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
Expand All @@ -241,8 +249,8 @@ DataDecoders: for iCh in 2 downto 0 generate
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChRdy(1 downto 0) => OtherChRdy(iCh), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => OtherChVld(iCh), -- tie channels together for channel de-skew

pC0 => pC0(iCh),
pC1 => pC1(iCh),
Expand Down