GNN4IC

Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.

Contributed by Lilas Alrahis, Johann Knechtel, and Ziad El Sayed.

Please note, the following list is just a collection of papers in no particular order.

Content

1. GNNs for EDA

1.1 Behavioral and Logic Design

1.2 Logic Synthesis

1.3 Partitioning and Floorplanning

1.4 Placement and Routing

1.5 Timing Closure

1.6 Verification and Testing

1.7 Analog, Mixed Signal, and Transistor Design

1.8 Circuit Design Completion

2. GNNs for Hardware Reliability

2.1 Aging Delay Prediction

2.2 Functional De-Rating Prediction

2.3 Critical Component Identification

2.4 Fault Diagnosis and Evaluation

3. GNNs for Hardware Security

3.1 HT Detection

3.2 Piracy Detection

3.3 Functional Reverse Engineering

3.4 Attacks on Design-for-Trust Methods

3.4.1 Key Leakage

3.4.2 Link Formation

3.4.3 Structural Leakage

3.4.4 Attack Scalability

3.4.5 Attack Sensitivity

GNNs for EDA

Behavioral and Logic Design

• IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022. paper

  Nan Wu, Yuan Xie, Cong Hao.

• IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning. Great Lakes Symposium on VLSI (GLVLSI), 2021. paper

  Nan Wu, Yuan Xie, Cong Hao.

• Graph Neural Networks for High-Level Synthesis Design Space Exploration. ACM Transactions on Design Automation of Electronic Systems, 2022. paper

  Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi.

• Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. International Conference on Computer-Aided Design (ICCAD), 2020. paper

  Ecenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li, Zhiru Zhang.

• Applying GNNs to Timing Estimation at RTL (Invited Paper). International Conference on Computer-Aided Design (ICCAD), 2022. paper

  Daniela Sánchez Lopera, Wolfgang Ecker.

• DeepGate: Learning Neural Representations of Logic Gates. Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC), 2022. paper

  Min Li, Sadaf Khan, Zhengyuan Shi, Naixing Wang, Huang Yu, Qiang Xu.

• DeepSeq: Deep Sequential Circuit Learning. IEEE, 2023. paper

  Sadaf Khan, Zhengyuan Shi, Min Li, Qiang Xu.

• Versatile Multi-Stage Graph Neural Network for Circuit Representation. Advances in Neural Information Processing Systems (NeurIPS), 2022. paper

  Shuwen Yang, Zhihao Yang, Dong Li, Yingxue Zhang, Zhanguang Zhang, Guojie Song, Jianye Hao.

Logic Synthesis

• CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks. VLSI-SoC, 2019. paper

  Robert Kirby, Saad Godil, Rajarshi Roy, Bryan Catanzaro.

• Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction. International Conference on Computer-Aided Design (ICCAD), 2021. paper

  Amur Ghose, Vincent Zhang, Yingxue Zhang, Dong Li, Wulong Liu, Mark Coates.

• Heterogeneous Graph Neural Network-based Imitation Learning for Gate Sizing Acceleration. International Conference on Computer-Aided Design (ICCAD), 2022. paper

  Xinyi Zhou, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang, Jianye Hao, Guangyong Chen, Pheng Ann Heng.

• LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models. Application-Specific Systems, Architectures and Processors (ASAP), 2022. paper

  Nan Wu, Jiwon Lee, Yuan Xie, Cong Hao.

• Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023. paper

  Sayandip De, Muhammad Shafique, Henk Corporaal.

• BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024. paper

  Yingjie Li, Anthony Agnesina, Yanqing Zhang, Haoxing Ren, Cunxi Yu.

Partitioning and Floorplanning

• TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs. Design Automation Conference (DAC), 2020. paper

  Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, Sung Kyu Lim.

• A Graph Placement Methodology for Fast Chip Design. Nature, 2021. paper

  Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nova, Jiwoo Pak, Andy Tong, Kavya Srinivasa, William Hang, Emre Tuncer, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter, Jeff Dean.

• GraphPlanner: Floorplanning with Graph Neural Network. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2022. paper

  Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang.

• GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning. IEEE Transactions on Artificial Intelligence, 2023. paper

  Xuenong Hong, Tong Lin, Yiqiong Shi, Bah Hwee Gwee.

• DeepTH: Chip Placement with Deep Reinforcement Learning Using a Three-Head Policy Network. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023. paper

  Dengwei Zhao, Shuai Yuan, Yanan Sun, Shikui Tu, Lei Xu.

Placement and Routing

• Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. Asia and South Pacific Design Automation Conference (ASP-DAC), 2021. paper

  Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen.

• VLSI Placement Optimization using Graph Neural Networks. Advances in Neural Information Processing Systems (NeurIPS), 2020. paper

  Yi-Chen Lu, Sai Pentapati, Sung Kyu Lim.

• The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks. International Symposium on Physical Design (ISPD), 2021. paper

  Yi-Chen Lu, Sai Pentapati, Sung Kyu Lim.

• VLSI Placement Parameter Optimization using Deep Reinforcement Learning. International Conference on Computer-Aided Design (ICCAD), 2020. paper

  Anthony Agnesina, Kyungwook Chang, Sung Kyu Lim.

• A General Framework for VLSI Tool Parameter Optimization with Deep Reinforcement Learning. Advances in Neural Information Processing Systems (NeurIPS), 2020. paper

  Anthony Agnesina, Sai Pentapati, Sung Kyu Lim.

• A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction. Design Automation Conference (DAC), 2022. paper

  Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin.

• Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net. International Conference on Computer-Aided Design (ICCAD), 2022. paper

  Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, Taewhan Kim.

• On Joint Learning for Solving Placement and Routing in Chip Design. Advances in Neural Information Processing Systems (NeurIPS), 2021. paper

  Ruoyu Cheng, Junchi Yan.

• A Learning-Based Algorithm for Early Floorplan With Flexible Blocks. IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022. paper

  Jen-Wei Lee, Yi-Ying Liao, Te-Wei Chen, Yu-Hsiu Lin, Chia-Wei Chen, Chun-Ku Ting, Sheng-Tai Tseng, Ronald Kuo-Hua Ho, Hsin-Chuan Kuo, Chun-Chieh Wang, Ming-Fang Tsai, Chun-Chih Yang, Tai-Lai Tung, Da-Shan Shiu.

• Detailed Routing Short Violation Prediction Using Graph-Based Deep Learning Model. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022. paper

  X. Chen, Z. Di, W. Wu, Q. Wu, J. Shi, Q. Feng.

• Reinforcement Learning Guided Detailed Routing for Custom Circuits. International Symposium on Physical Design (ISPD), 2023. paper

  Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing Ren.

Timing Closure

• RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. Design Automation Conference (DAC), 2021. paper

  Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim.

• Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. International Conference on Computer-Aided Design (ICCAD), 2021. paper

  Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim.

• Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis. Asia and South Pacific Design Automation Conference (ASP-DAC), 2023. paper

  Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi.

• SyncTREE: Fast Timing Analysis for Integrated Circuit Design through a Physics-Informed Tree-Based Graph Neural Network. Advances in Neural Information Processing Systems (NeurIPS), 2024. paper

  Yuting Hu, Jiajie Li, Florian Klemme, Gi-Joon Nam, Tengfei Ma, Hussam Amrouch, Jinjun Xiong.

Verification and Testing

• GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. Design Automation Conference (DAC), 2020. paper

  Yanqing Zhang, Haoxing Ren, Brucek Khailany.

• High Performance Graph Convolutional Networks with Applications in Testability Analysis. Design Automation Conference (DAC), 2019. paper

  Y. Ma, H. Ren, B. Khailany, H. Sikka, L. Luo, K. Natarajan, B. Yu.

• DeepTPI: Test Point Insertion with Deep Reinforcement Learning. IEEE International Test Conference (ITC), 2022. paper

  Zhengyuan Shi, Min Li, Sadaf Khan, Liuzheng Wang, Naixing Wang, Yu Huang.

• RC-GNN: Fast and Accurate Signoff Wire Delay Estimation with Customized Graph Neural Networks. IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023. paper

  Linyu Zhu, Yue Gu, Xinfei Guo.

• Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023. paper

  Shao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Sung Kyu Lim, Krishnendu Chakrabarty.

• GRAND: A Graph Neural Network Framework for Improved Diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024. paper

  Hongfei Wang, Ziqiang Zhang, Hongcan Xiong, Dongmian Zou, Yu Chen, Hai Jin.

Analog, Mixed Signal, and Transistor Design

• Circuit-GNN: Graph Neural Networks for Distributed Circuit Design. International Conference on Machine Learning (ICML), 2019. paper

  Guo Zhang, Hao He, Dina Katabi.

• ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks. Design Automation Conference (DAC), 2020. paper

  Haoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku.

• GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. Design Automation Conference (DAC), 2020. paper

  Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han.

• Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. ACM/IEEE Design Automation Conference (DAC), 2021. paper

  Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan.

• CktGNN: Circuit Graph Neural Network for Electronic Design Automation. International Conference on Learning Representations (ICLR), 2023. paper

  Zehao Dong, Weidong Cao, Muhan Zhang, Dacheng Tao, Yixin Chen, Xuan Zhang.

• Graph of Circuits with GNN for Exploring the Optimal Design Space. Advances in Neural Information Processing Systems (NeurIPS), 2024. paper

  Aditya Hemant Shahane, Swapna Manjiri, Ankesh Jain, Ankesh Jain.

• GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023. paper

  Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar.

Circuit Design Completion

• Circuit Design Completion Using Graph Neural Networks. Neural Computing and Applications, 2023. paper

  Anwar Said, Mudassir Shabbir, Brian Broll, Waseem Abbas, Peter Völgyesi, Xenofon Koutsoukos.

GNNs for Hardware Reliability

Aging Delay Prediction

• GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022. paper

  Lilas Alrahis, Johann Knechtel, Florian Klemme, Hussam Amrouch, Ozgur Sinanoglu.

• Analog IC Aging-Induced Degradation Estimation via Heterogeneous Graph Convolutional Networks. Asia and South Pacific Design Automation Conference (ASP-DAC), 2021. paper

  Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu.

• Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022. paper

  Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu.

• Fast Aging-Aware Timing Analysis Framework with Temporal–Spatial Graph Neural Network. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023. paper

  Jinfeng Ye, Pengpeng Ren, Yongkang Xue, Hui Fang, Zhigang Ji.

Functional De-Rating Prediction

• Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2019. paper

  Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin.

Critical Component Identification

• Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023. paper

  Li Lu, Junchao Chen, Markus Ulbricht, Milos Krstic.

• Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024. paper

  Tarek Mohamed, Victor M. van Santen, Lilas Alrahis, Ozgur Sinanoglu, Hussam Amrouch.

Fault Diagnosis and Evaluation

• An Intelligent Fault Detection Approach for Digital Integrated Circuits Through Graph Neural Networks. Mathematical Biosciences and Engineering, 2023. paper

  Zulin Xu.

• On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023. paper

  Amalia-Artemis Koufopoulou, Athanasios Papadimitriou, Aggelos Pikrakis, Mihalis Psarakis, David Hely.

GNNs for Hardware Security

HT Detection

• GNN4TJ: Graph Neural Networks for Hardware Trojan Detection at Register Transfer Level. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. paper

  Rozhin Yasaei, Shih-Yuan Yu, Mohammad Abdullah Al Faruque.

• Hardware Trojan Detection Using Graph Neural Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022. paper

  Rozhin Yasaei, Luke Chen, Shih-Yuan Yu, Mohammad Abdullah Al Faruque.

• HW2VEC: A Graph Learning Tool for Automating Hardware Security. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2021. paper

  Shih-Yuan Yu, Rozhin Yasaei, Qingrong Zhou, Tommy Nguyen, Mohammad Abdullah Al Faruque.

• Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2022. paper

  Rozhin Yasaei, Sina Faezi, Mohammad Abdullah Al Faruque.

• Contrastive Graph Convolutional Networks for Hardware Trojan Detection in Third-Party IP Cores. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2021. paper

  Nikhil Muralidhar, Abdullah Zubair, Nathanael Weidler, Ryan Gerdes, Naren Ramakrishnan.

• BGNN-HT: Bidirectional Graph Neural Network for Hardware Trojan Cells Detection at Gate Level. IEEE International Symposium on Circuits and Systems (ISCAS), 2023. paper

  Peiheng Zhan, Haihua Shen, Shan Li, Huawei Li.

• A Fine-Grained Detection Method for Gate-Level Hardware Trojan Based on Bidirectional Graph Neural Networks. Journal of King Saud University-Computer and Information Sciences, 2023. paper

  Dong Cheng, Chen Dong, Wenwu He, Zhenyi Chen, Ximeng Liu, Hao Zhang.

• A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans. Cryptology ePrint Archive, 2023. paper

  Xingyu Meng, Abhrajit Sengupta, Kanad Basu.

• A Unioned Graph Neural Network Based Hardware Trojan Node Detection. IEICE Electronics Express, 2023. paper

  Weitao Pan, Meng Dong, Cong Wen, Hongjin Liu, Shaolin Zhang, Bo Shi, Zhixiong Di, Zhiliang Qiu, Yiming Gao, Ling Zheng.

• Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023. paper

  Rakibul Hassan, Xingyu Meng, Kanad Basu, Sai Manoj Pudukotai Dinakarrao.

• MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2024. paper

  Lilas Alrahis, Hassan Nassar, Jonas Krautter, Dennis Gnad, Lars Bauer, Jörg Henkel.

Piracy Detection

• GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection. Design Automation Conference (DAC), 2021. paper

  Rozhin Yasaei, Shih-Yuan Yu, Emad Kasaeyan Naeini, Mohammad Abdullah Al Faruque.

• HW2VEC: A Graph Learning Tool for Automating Hardware Security. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2021. paper

  Shih-Yuan Yu, Rozhin Yasaei, Qingrong Zhou, Tommy Nguyen, Mohammad Abdullah Al Faruque.

• PoisonedGNN: Backdoor Attack on Graph Neural Networks-Based Hardware Security Systems. IEEE Transactions on Computers, 2023. paper

  Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu.

• GoCLIP: Graph One-Class Classification for Intellectual Property Circuit Identification. IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2023. paper

  Xuenong Hong, Yee-Yang Tee, Tong Lin, Yiqiong Shi, Deruo Cheng, Erdong Huang.

Functional Reverse Engineering

• GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022. paper

  Lilas Alrahis, Abhrajit Sengupta, Johann Knechtel, Satwik Patnaik, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu.

• Gamora: Graph Learning-Based Symbolic Reasoning for Large-Scale Boolean Networks. IEEE, 2023. paper

  Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, Yuan Xie.

• DepthGraphNet: Circuit Graph Isomorphism Detection via Siamese-Graph Neural Networks. ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), 2023. paper

  Fin Amin, Soumyadeep Chatterjee, Paul D. Franzon.

• ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineering. International Conference on Computer-Aided Design (ICCAD), 2021. paper

  Subhajit Dutta Chowdhury, Kaixin Yang, Pierluigi Nuzzo.

• Graph Learning-Based Arithmetic Block Identification. International Conference on Computer-Aided Design (ICCAD), 2021. paper

  Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu.

• Functionality Matters in Netlist Representation Learning. Design Automation Conference (DAC), 2022. paper

  Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang.

• ConVERTS: Contrastively Learning Structurally Invariant Netlist Representations. ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), 2023. paper

  Animesh B. Chowdhury, Jitendra Bhandari, Luca Collini, Ramesh Karri, Benjamin Tan, Siddharth Garg.

• Graph Neural Network-Based Netlist Operator Detection Under Circuit Rewriting. Great Lakes Symposium on VLSI (GLSVLSI), 2022. paper

  Guangwei Zhao, Kaveh Shamsi.

• AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural Networks. International Conference on Computer-Aided Design (ICCAD), 2022. paper

  Tim Bücher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, Hussam Amrouch.

• GANA: Graph Convolutional Network-Based Automated Netlist Annotation for Analog Circuits. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020. paper

  Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar.

Attacks on Design-for-Trust Methods

Key Leakage

• OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking. IEEE Transactions on Circuits and Systems II (TCAS-II), 2022. paper

  Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu.

Link Formation

• MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-Based Link Prediction. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022. paper

  Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu.

• UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-Based Link Prediction. International Conference on Computer-Aided Design (ICCAD), 2021. paper

  Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu.

Structural Leakage

• Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2021. paper

  Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers.

• SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2021. paper

  Abdulrahman Alaql, Md Moshiur Rahman, Swarup Bhunia.

• InterLock: An Intercorrelated Logic and Routing Locking. International Conference on Computer-Aided Design (ICCAD), 2020. paper

  Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan.

Attack Scalability

• Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks. IEEE Transactions on Information Forensics and Security (TIFS), 2022. paper

  Likhitha Mankali, Lilas Alrahis, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu.

• UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks. International Conference on Security, Privacy, and Applied Cryptography Engineering, 2023. paper

  Lilas Alrahis, Likhitha Mankali, Satwik Patnaik, Abhrajit Sengupta, Johann Knechtel, Ozgur Sinanoglu.

• GNNUnlock: Graph Neural Networks-Based Oracle-Less Unlocking Scheme for Provably Secure Logic Locking. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. paper

  Lilas Alrahis, Satwik Patnaik, Faiq Khalid, Muhammad Abdullah Hanif, Hani Saleh, Muhammad Shafique, Ozgur Sinanoglu.

• Estimating the Circuit De-Obfuscation Runtime Based on Graph Deep Learning. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020. paper

  Zhiqian Chen, Gaurav Kolhe, Setareh Rafatirad, Chang-Tien Lu, Sai Manoj P.D., Houman Homayoun, Liang Zhao.

Attack Sensitivity

• NetlistGNN: Characterizing the Ability of GNNs in Attacking Logic Locking. ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), 2023. paper

  Wei Li, Ruben Purdy, José M. F. Moura, R.D. Blanton.