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Fix inconsistencies with schematics
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Signed-off-by: Michał Żygowski <[email protected]>
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@miczyg1
miczyg1 committed Sep 16, 2024
1 parent 0bbd8df commit ce4e8e3
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Showing 7 changed files with 120 additions and 125 deletions.
106 changes: 39 additions & 67 deletions src/mainboard/clevo/mtl-h/devicetree.cb
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Original file line number Diff line number Diff line change
Expand Up @@ -26,61 +26,33 @@ chip soc/intel/meteorlake
register "pch_pm_energy_report_enable" = "1"

# Thermal
register "tcc_offset" = "30" # TCC of 100C
register "tcc_offset" = "30" # TCC of 80C

# Power limits
# Power limits,
# PsysPL2, PsysPL3, PL4 are configured by EC at runtime
register "power_limits_config[MTL_P_682_482_CORE]" = "{
.tdp_pl1_override = 35,
.tdp_pl2_override = 64,
.tdp_pl4 = 120,
.psys_pmax = 180,
}"

register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC_SKIP), /* USB Type-A Port 1 (Left) */
[1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */
[2] = USB2_PORT_MID(OC_SKIP), /* USB Type-A Port 2 (Right) */
[5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */
[6] = USB2_PORT_LONG(OC_SKIP), /* Integrated Camera */
[9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth on M.2 2230 */
}"

register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */
}"

register "tcss_ports" = "{
[0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */
[1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */
}"

# SOC Aux orientation override:
# This is a bitfield that corresponds to up to 4 TCSS ports.
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
# Bits (4,5) allocated for TCSS Port3 configuration and Bits (6,7)for TCSS Port4.
# Bit0,Bit2,Bit4,Bit6 set to "1" indicates no retimer on USBC Ports
# Bit1,Bit3,Bit5,Bit7 set to "0" indicates Aux lines are not swapped on the
# motherboard to USBC connector
register "tcss_aux_ori" = "0x54"
# MTL SOC has additional setting for PsysPmax
register "psys_pmax_watts" = "180"

device cpu_cluster 0 on end
device domain 0 on
device ref system_agent on end
device ref igpu on
register "ddi_port_A_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */
[DDI_PORT_2] = DDI_ENABLE_DDC | DDI_ENABLE_HPD, /* HDMI 2.1 */
}"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref dtt on end
device ref pcie_rp10 on # M.2 2280 #2
register "pcie_rp[PCH_RP(10)]" = "{
.clk_src = 8,
.clk_req = 8,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
Expand All @@ -95,7 +67,7 @@ chip soc/intel/meteorlake
register "pcie_rp[PCH_RP(11)]" = "{
.clk_src = 7,
.clk_req = 7,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
Expand All @@ -111,6 +83,21 @@ chip soc/intel/meteorlake
device ref crashlog on end
device ref vpu on end
device ref tcss_xhci on

# SOC Aux orientation override:
# This is a bitfield that corresponds to up to 4 TCSS ports.
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
# Bits (4,5) allocated for TCSS Port3 configuration and Bits (6,7)for TCSS Port4.
# Bit0,Bit2,Bit4,Bit6 set to "1" indicates no retimer on USBC Ports
# Bit1,Bit3,Bit5,Bit7 set to "0" indicates Aux lines are not swapped on the
# motherboard to USBC connector
register "tcss_aux_ori" = "0x54"

register "tcss_ports" = "{
[0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */
[1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */
}"

chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
Expand Down Expand Up @@ -139,6 +126,21 @@ chip soc/intel/meteorlake
end
device ref ioe_shared_sram on end
device ref xhci on

register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC_SKIP), /* USB Type-A Port 1 (Left) */
[1] = USB2_PORT_MID(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */
[2] = USB2_PORT_MID(OC_SKIP), /* USB Type-A Port 2 (Right) */
[5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */
[6] = USB2_PORT_LONG(OC_SKIP), /* Integrated Camera */
[9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth on M.2 2230 */
}"

register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */
}"

chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
Expand Down Expand Up @@ -208,38 +210,14 @@ chip soc/intel/meteorlake
device generic 0 on end
end
end
device ref i2c0 on # Touchpad
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref i2c1 on # USB-PD EEPROM
register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref i2c3 on # Pantone ROM
register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
end
device ref pcie_rp5 on # GLAN
register "pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
}"
register "pcie_clk_config_flag[2]" = "PCIE_CLK_LAN"
device ref i2c5 on # Smart AMP
register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
end
device ref pcie_rp6 on # SD Card Reader
register "pcie_rp[PCH_RP(6)]" = "{
Expand Down Expand Up @@ -288,12 +266,6 @@ chip soc/intel/meteorlake
use tcss_usb3_port0 as usb3_port
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
# USB Type-C Port 2 (Non-TBT)
use usb2_port2 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 1 alias conn1 on end
end
end
end
end
Expand Down
15 changes: 13 additions & 2 deletions src/mainboard/clevo/mtl-h/ramstage.c
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Original file line number Diff line number Diff line change
Expand Up @@ -203,9 +203,20 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
// Enable reporting CPU C10 state over eSPI
params->PchEspiHostC10ReportEnable = 1;

params->PchSerialIoI2cSdaPinMux[3] = 0x1A45CA06; // GPP_H6
params->PchSerialIoI2cSclPinMux[3] = 0x1A45AA07; // GPP_H7

params->PchSerialIoI2cSdaPinMux[4] = 0x8A44CC0C; // GPP_E12
params->PchSerialIoI2cSclPinMux[4] = 0x8A44AC0D; // GPP_E13

params->PchSerialIoI2cSdaPinMux[5] = 0x8A46CE0D; // GPP_F13
params->PchSerialIoI2cSclPinMux[5] = 0x8A46AE0C; // GPP_F12

// Pinmux configuration
params->CnviRfResetPinMux = 0x194CE404; // GPP_F04
params->CnviClkreqPinMux = 0x394CE605; // GPP_F05
params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
params->CnviClkreqPinMux = 0x394CE605; // GPP_F5

params->EnableTcssCovTypeA[1] = 1;

params->LidStatus = system76_ec_get_lid_state();
}
100 changes: 50 additions & 50 deletions src/mainboard/clevo/mtl-h/variants/dgpu/gpio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ static const struct pad_config gpio_table[] = {
/* ------- GPIO Group V ------- */
PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), /* BATLOW# */
PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), /* ACPRESENT */
PAD_CFG_GPI_TRIG_OWN(GPP_V02, NATIVE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_V02, NATIVE, DEEP, OFF, ACPI), /* GPIO - CPU_LAN_WAKEUP# */
PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), /* PWRBTN# */
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* SLP_S3# */
PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), /* SLP_S4# */
Expand All @@ -24,7 +24,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), /* SUSCLK */
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), /* SLP_WLAN# */
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), /* SLP_S5# */
PAD_CFG_GPO(GPP_V11, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_V11, 1, DEEP), /* GPIO - GPIO_LAN_EN */
PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), /* SLP_LAN# */
PAD_CFG_GPO(GPP_V13, 0, DEEP), /* GPIO */
PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* WAKE# */
Expand Down Expand Up @@ -54,7 +54,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* SRCCLKREQ3# */
PAD_CFG_GPO(GPP_C13, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_C14, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_DGPU_PWRGD */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TBT_LSX0_TXD */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TBT_LSX0_RXD */
PAD_CFG_GPO(GPP_C18, 0, DEEP), /* GPIO */
Expand All @@ -78,39 +78,39 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_A08, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_A09, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_A10, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_A11, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_A14, UP_20K, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_A15, 0, DEEP), /* GPIO */
PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), /* RSVD */
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL),
PAD_CFG_GPO(GPP_A18, 0, DEEP), /* GPIO */
PAD_CFG_GPI_APIC(GPP_A19, NONE, DEEP, LEVEL, NONE), /* GPIO */
PAD_CFG_GPO(GPP_A20, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_A11, 0, DEEP), /* GPIO - ADDS_CODE */
PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), /* GPIO - WLAN_WAKEUP# */
PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), /* GPIO - M2_SSD2_RST# */
PAD_CFG_GPI_TRIG_OWN(GPP_A14, UP_20K, DEEP, OFF, ACPI), /* GPIO - NVVDD_ALERT# */
PAD_CFG_GPO(GPP_A15, 0, DEEP), /* GPIO - CPU_SWI# */
PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), /* RSVD - ESPI_ALERT0# */
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), /* GPIO - TP_ATTN# */
PAD_CFG_GPO(GPP_A18, 0, DEEP), /* GPIO - TEST_R (ANX7411) */
PAD_CFG_GPI_APIC(GPP_A19, NONE, DEEP, LEVEL, NONE), /* GPIO - INTP_OUT (ANX7411) */
PAD_CFG_GPO(GPP_A20, 1, DEEP), /* GPIO - LAN_PLT_RST# */
PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), /* PMCALERT# */
PAD_NC(GPP_A22, NATIVE), /* GPIO */
PAD_NC(GPP_A23, NATIVE), /* GPIO */

/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_E00, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E00, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID7 */
PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), /* GPIO - TPM_PIRQ# */
PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID4 */
PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_CNVI_WAKE# */
PAD_CFG_GPO(GPP_E04, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_E05, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_E07, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_E07, 0, DEEP), /* GPIO - CPU_SMI# */
PAD_CFG_GPO(GPP_E08, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_E09, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_E10, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID6 */
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), /* I2C4_SDA - ANX7411 */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), /* I2C4_SCL - ANX7411 */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */
PAD_CFG_GPO(GPP_E15, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_E15, 0, DEEP), /* GPIO - CPU_SCI# */
PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), /* VRALERT# */
PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID5 */
PAD_CFG_GPO(GPP_E18, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_E19, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_E20, 0, DEEP), /* GPIO */
Expand Down Expand Up @@ -156,19 +156,19 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */
PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), /* CNV_RF_RESET# */
PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), /* MODEM_CLKREQ */
PAD_NC(GPP_F06, NONE), /* GPIO */
PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), /* CNVI_GNSS_PA_BLANKING */
PAD_CFG_GPO(GPP_F07, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_F08, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), /* GPIO - TPM_DET */
PAD_CFG_GPO(GPP_F10, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* I2C5_SCL */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* I2C5_SDA */
PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID3 */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* I2C5_SCL - Smart AMP */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* I2C5_SDA - Smart AMP */
PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID1 */
PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID2 */
PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), /* GPIO - GPIO4_GC6_NVVDD_EN */
PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), /* GPIO - CPU_GC6_FB_EN */
PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPIO -CCD_WP# */
PAD_CFG_GPO(GPP_F19, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_F20, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_F21, 0, DEEP), /* GPIO */
Expand Down Expand Up @@ -217,34 +217,34 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_B02, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B03, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B04, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B05, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B06, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B07, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B08, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B09, 0, DEEP), /* GPIO */
PAD_CFG_GPI_SCI(GPP_B10, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO */
PAD_CFG_GPI_SCI(GPP_B11, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO */
PAD_CFG_GPO(GPP_B05, 0, DEEP), /* GPIO - CPU_KBCRST# */
PAD_CFG_GPO(GPP_B06, 0, DEEP), /* GPIO - ROM_I2C_EN */
PAD_CFG_GPO(GPP_B07, 0, DEEP), /* GPIO - PANTONE_WP# */
PAD_CFG_GPO(GPP_B08, 0, DEEP), /* GPIO - PS8461_SW (DDS for eDP) */
PAD_CFG_GPO(GPP_B09, 0, DEEP), /* GPIO - DGPU_RST#_PCH */
PAD_CFG_GPI_SCI(GPP_B10, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV Type-C DP HPD */
PAD_CFG_GPI_SCI(GPP_B11, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV HDMI HPD */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */
PAD_CFG_GPO(GPP_B14, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_B16, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B18, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GPIO - CPU_GPIO_LANRTD3 */
PAD_CFG_GPO(GPP_B18, 1, DEEP), /* GPIO - PCH_BT_EN */
PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPIO - WIFI_RF_EN */
PAD_CFG_GPO(GPP_B20, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* GPIO - TBT_FORCE_PWR */
PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPIO */
PAD_CFG_TERM_GPO(GPP_B23, 0, DN_20K, DEEP), /* GPIO */
PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), /* n/a */

/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D00, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D01, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D02, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D03, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D00, 1, DEEP), /* GPIO - SB_BLON */
PAD_CFG_GPO(GPP_D01, 1, DEEP), /* GPIO - SSD2_PWR_EN */
PAD_CFG_GPO(GPP_D02, 1, DEEP), /* GPIO - M2_SSD1_RST# */
PAD_CFG_GPO(GPP_D03, 0, DEEP), /* GPIO - CPU_DGPU_PWR_EN */
PAD_CFG_GPO(GPP_D04, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D05, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D05, 1, DEEP), /* GPIO - SSD1_PWR_EN */
PAD_CFG_GPO(GPP_D06, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D07, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D08, 0, DEEP), /* GPIO */
Expand All @@ -255,7 +255,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), /* HDA_SDI0 */
PAD_CFG_GPO(GPP_D14, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D15, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D16, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_D16, 0, DEEP), /* GPIO - GPIO_SPK_MUTE */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* HDA_RST# */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* SRCCLKREQ6# */
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* SRCCLKREQ7# */
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7 changes: 5 additions & 2 deletions src/mainboard/clevo/mtl-h/variants/dgpu/overridetree.cb
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,9 @@ chip soc/intel/meteorlake
device i2c 38 on end
end
end
device ref i2c4 on # ANX7443 USB-C Retimer
register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
end
device ref i2c5 on # TAS5825M SmartAmp
register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
chip drivers/i2c/tas5825m
Expand All @@ -47,10 +50,10 @@ chip soc/intel/meteorlake
register "pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B17)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_V11)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
register "srcclk_pin" = "2"
device generic 0 on end
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