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net/e1000: support launchtime feature
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Enable the time-based scheduled Tx of packets based on the
RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP flag. The launchtime defines the
packet transmission time based on PTP clock at MAC layer, which should
be set to the advanced transmit descriptor.

Signed-off-by: Chuanyu Xue <[email protected]>
Reviewed-by: Simei Su <[email protected]>
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@ChuanyuXue @qzhan16
ChuanyuXue authored and qzhan16 committed Jan 5, 2024
1 parent 58182a1 commit 28717cb
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Showing 4 changed files with 112 additions and 8 deletions.
1 change: 1 addition & 0 deletions drivers/net/e1000/base/e1000_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -162,6 +162,7 @@

/* QAV Tx mode control register */
#define E1000_I210_TQAVCTRL 0x3570
#define E1000_I210_LAUNCH_OS0 0x3578

/* QAV Tx mode control register bitfields masks */
/* QAV enable */
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14 changes: 14 additions & 0 deletions drivers/net/e1000/e1000_ethdev.h
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Original file line number Diff line number Diff line change
Expand Up @@ -382,6 +382,20 @@ extern struct igb_rss_filter_list igb_filter_rss_list;
TAILQ_HEAD(igb_flow_mem_list, igb_flow_mem);
extern struct igb_flow_mem_list igb_flow_list;

/*
* Macros to compensate the constant latency observed in i210 for launch time
*
* launch time = (offset_speed - offset_base + txtime) * 32
* offset_speed is speed dependent, set in E1000_I210_LAUNCH_OS0
*/
#define IGB_I210_TX_OFFSET_BASE 0xffe0
#define IGB_I210_TX_OFFSET_SPEED_10 0xc7a0
#define IGB_I210_TX_OFFSET_SPEED_100 0x86e0
#define IGB_I210_TX_OFFSET_SPEED_1000 0xbe00

extern uint64_t igb_tx_timestamp_dynflag;
extern int igb_tx_timestamp_dynfield_offset;

extern const struct rte_flow_ops igb_flow_ops;

/*
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63 changes: 62 additions & 1 deletion drivers/net/e1000/igb_ethdev.c
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Original file line number Diff line number Diff line change
Expand Up @@ -223,6 +223,7 @@ static int igb_timesync_read_time(struct rte_eth_dev *dev,
struct timespec *timestamp);
static int igb_timesync_write_time(struct rte_eth_dev *dev,
const struct timespec *timestamp);
static int eth_igb_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
uint16_t queue_id);
static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
Expand Down Expand Up @@ -313,6 +314,9 @@ static const struct rte_pci_id pci_id_igbvf_map[] = {
{ .vendor_id = 0, /* sentinel */ },
};

uint64_t igb_tx_timestamp_dynflag;
int igb_tx_timestamp_dynfield_offset = -1;

static const struct rte_eth_desc_lim rx_desc_lim = {
.nb_max = E1000_MAX_RING_DESC,
.nb_min = E1000_MIN_RING_DESC,
Expand Down Expand Up @@ -389,6 +393,7 @@ static const struct eth_dev_ops eth_igb_ops = {
.timesync_adjust_time = igb_timesync_adjust_time,
.timesync_read_time = igb_timesync_read_time,
.timesync_write_time = igb_timesync_write_time,
.read_clock = eth_igb_read_clock,
};

/*
Expand Down Expand Up @@ -1188,6 +1193,40 @@ eth_igb_rxtx_control(struct rte_eth_dev *dev,
E1000_WRITE_FLUSH(hw);
}


static uint32_t igb_tx_offset(struct rte_eth_dev *dev)
{
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);

uint16_t duplex, speed;
hw->mac.ops.get_link_up_info(hw, &speed, &duplex);

uint32_t launch_os0 = E1000_READ_REG(hw, E1000_I210_LAUNCH_OS0);
if (hw->mac.type != e1000_i210) {
/* Set launch offset to base, no compensation */
launch_os0 |= IGB_I210_TX_OFFSET_BASE;
} else {
/* Set launch offset depend on link speeds */
switch (speed) {
case SPEED_10:
launch_os0 |= IGB_I210_TX_OFFSET_SPEED_10;
break;
case SPEED_100:
launch_os0 |= IGB_I210_TX_OFFSET_SPEED_100;
break;
case SPEED_1000:
launch_os0 |= IGB_I210_TX_OFFSET_SPEED_1000;
break;
default:
launch_os0 |= IGB_I210_TX_OFFSET_BASE;
break;
}
}

return launch_os0;
}

static int
eth_igb_start(struct rte_eth_dev *dev)
{
Expand All @@ -1198,6 +1237,7 @@ eth_igb_start(struct rte_eth_dev *dev)
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int ret, mask;
uint32_t tqavctrl;
uint32_t intr_vector = 0;
uint32_t ctrl_ext;
uint32_t *speeds;
Expand Down Expand Up @@ -1273,6 +1313,15 @@ eth_igb_start(struct rte_eth_dev *dev)

eth_igb_tx_init(dev);

if (igb_tx_timestamp_dynflag > 0) {
tqavctrl = E1000_READ_REG(hw, E1000_I210_TQAVCTRL);
tqavctrl |= E1000_TQAVCTRL_MODE; /* Enable Qav mode */
tqavctrl |= E1000_TQAVCTRL_FETCH_ARB; /* ARB fetch, no Round Robin*/
tqavctrl |= E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE; /* Enable Tx launch time*/
E1000_WRITE_REG(hw, E1000_I210_TQAVCTRL, tqavctrl);
E1000_WRITE_REG(hw, E1000_I210_LAUNCH_OS0, igb_tx_offset(dev));
}

/* This can fail when allocating mbufs for descriptor rings */
ret = eth_igb_rx_init(dev);
if (ret) {
Expand Down Expand Up @@ -1393,7 +1442,6 @@ eth_igb_start(struct rte_eth_dev *dev)

eth_igb_rxtx_control(dev, true);
eth_igb_link_update(dev, 0);

PMD_INIT_LOG(DEBUG, "<<");

return 0;
Expand Down Expand Up @@ -4882,6 +4930,19 @@ igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
return 0;
}

static int
eth_igb_read_clock(struct rte_eth_dev *dev, uint64_t *clock)
{
struct e1000_adapter *adapter = dev->data->dev_private;
struct rte_timecounter *tc = &adapter->systime_tc;
uint64_t cycles;

cycles = igb_read_systime_cyclecounter(dev);
*clock = rte_timecounter_update(tc, cycles);

return 0;
}

static int
eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
{
Expand Down
42 changes: 35 additions & 7 deletions drivers/net/e1000/igb_rxtx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -244,12 +244,13 @@ check_tso_para(uint64_t ol_req, union igb_tx_offload ol_para)
static inline void
igbe_set_xmit_ctx(struct igb_tx_queue* txq,
volatile struct e1000_adv_tx_context_desc *ctx_txd,
uint64_t ol_flags, union igb_tx_offload tx_offload)
uint64_t ol_flags, union igb_tx_offload tx_offload, uint64_t txtime)
{
uint32_t type_tucmd_mlhl;
uint32_t mss_l4len_idx;
uint32_t ctx_idx, ctx_curr;
uint32_t vlan_macip_lens;
uint32_t launch_time;
union igb_tx_offload tx_offload_mask;

ctx_curr = txq->ctx_curr;
Expand Down Expand Up @@ -312,16 +313,25 @@ igbe_set_xmit_ctx(struct igb_tx_queue* txq,
}
}

txq->ctx_cache[ctx_curr].flags = ol_flags;
txq->ctx_cache[ctx_curr].tx_offload.data =
tx_offload_mask.data & tx_offload.data;
txq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;
if (!txtime) {
txq->ctx_cache[ctx_curr].flags = ol_flags;
txq->ctx_cache[ctx_curr].tx_offload.data =
tx_offload_mask.data & tx_offload.data;
txq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;
}

ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
vlan_macip_lens = (uint32_t)tx_offload.data;
ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
ctx_txd->u.seqnum_seed = 0;

if (txtime) {
launch_time = (txtime - IGB_I210_TX_OFFSET_BASE) % NSEC_PER_SEC;
ctx_txd->u.launch_time = rte_cpu_to_le_32(launch_time / 32);
} else {
ctx_txd->u.launch_time = 0;
}
}

/*
Expand Down Expand Up @@ -400,6 +410,7 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint32_t new_ctx = 0;
uint32_t ctx = 0;
union igb_tx_offload tx_offload = {0};
uint64_t ts;

txq = tx_queue;
sw_ring = txq->sw_ring;
Expand Down Expand Up @@ -552,7 +563,13 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
txe->mbuf = NULL;
}

igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload);
if (igb_tx_timestamp_dynflag > 0) {
ts = *RTE_MBUF_DYNFIELD(tx_pkt,
igb_tx_timestamp_dynfield_offset, uint64_t *);
igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload, ts);
} else {
igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload, 0);
}

txe->last_id = tx_last;
tx_id = txe->next_id;
Expand Down Expand Up @@ -1464,7 +1481,8 @@ igb_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
RTE_ETH_TX_OFFLOAD_TCP_TSO |
RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP;

return tx_offload_capa;
}
Expand Down Expand Up @@ -2579,9 +2597,11 @@ eth_igb_tx_init(struct rte_eth_dev *dev)
{
struct e1000_hw *hw;
struct igb_tx_queue *txq;
uint64_t offloads = dev->data->dev_conf.txmode.offloads;
uint32_t tctl;
uint32_t txdctl;
uint16_t i;
int err;

hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);

Expand Down Expand Up @@ -2612,6 +2632,14 @@ eth_igb_tx_init(struct rte_eth_dev *dev)
dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
}

if (offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) {
err = rte_mbuf_dyn_tx_timestamp_register(
&igb_tx_timestamp_dynfield_offset,
&igb_tx_timestamp_dynflag);
if (err)
PMD_DRV_LOG(ERR, "Failed to register tx timestamp dynamic field");
}

/* Program the Transmit Control Register. */
tctl = E1000_READ_REG(hw, E1000_TCTL);
tctl &= ~E1000_TCTL_CT;
Expand Down

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