Update Carpenter port

[apcraig]

PR checklist

• Short (1 sentence) summary of your PR:
  Update Carpenter port
• Developer(s):
  apcraig
• Suggest PR reviewers from list in the column to the right.
• Please copy the PR test results link or provide a summary of testing completed below.
  All test bit-for-bit, intel and intelimpi debug tests that were failing are now working. https://github.com/CICE-Consortium/Test-Results/wiki/cice_by_hash_forks#2cdd3d007a409d26cb0c16d946678a544ada55fa
• How much do the PR code changes differ from the unmodified code?
  • bit for bit
  • different at roundoff level
  • more substantial
• Does this PR create or have dependencies on Icepack or any other models?
  • Yes
  • No
• Does this PR update the Icepack submodule? If so, the Icepack submodule must point to a hash on Icepack's main branch.
  • Yes
  • No
• Does this PR add any new test cases?
  • Yes
  • No
• Is the documentation being updated? ("Documentation" includes information on the wiki or in the .rst files from doc/source/, which are used to create the online technical docs at https://readthedocs.org/projects/cice-consortium-cice/. A test build of the technical docs will be performed as part of the PR testing.)
  • Yes
  • No, does the documentation need to be updated at a later time?
    • Yes
    • No
• Please document the changes in detail, including why the changes are made. This will become part of the PR commit log.

Update the Carpenter port

• Update intel and intelimpi due to failures in debug mode associated with a compiler bug. Change -fpe0 to -fpe1. This has been a known testing issue for a while, it's overdue to be fixed.
• Update the intel and intelimpi modules to the latest, this is bit-for-bit.
• Add inteloneapi compiler