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fix: storage v2 #5027

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Merged
Maddiaa0 merged 12 commits into from
Mar 7, 2024
Merged

fix: storage v2 #5027

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389f14a
feat: avm storage
sirasistant Feb 14, 2024
bedc4f9
rebuild: avm
Maddiaa0 Mar 7, 2024
0949088
fix: revert risky storage oracle changes
Maddiaa0 Mar 7, 2024
2f6e86b
Merge branch 'master' into md/storage
Maddiaa0 Mar 7, 2024
e075c3b
fix: restore missing test
Maddiaa0 Mar 7, 2024
c4c3ce1
fix: config yml
Maddiaa0 Mar 7, 2024
befe4a0
fix: end to end deps
Maddiaa0 Mar 7, 2024
65110dc
fix: same for yarn project tests
Maddiaa0 Mar 7, 2024
ac777d6
Merge branch 'md/fix-e2e-2-electric-boogaloo' into md/storage
Maddiaa0 Mar 7, 2024
ee6178d
Merge branch 'master' into md/storage
Maddiaa0 Mar 7, 2024
e47dac7
fmt
Maddiaa0 Mar 7, 2024
a0d80c6
Merge branch 'master' into md/storage
Maddiaa0 Mar 7, 2024
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1 change: 1 addition & 0 deletions avm-transpiler/src/instructions.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ use crate::opcodes::AvmOpcode;
pub const ALL_DIRECT: u8 = 0b00000000;
pub const ZEROTH_OPERAND_INDIRECT: u8 = 0b00000001;
pub const FIRST_OPERAND_INDIRECT: u8 = 0b00000010;
pub const SECOND_OPERAND_INDIRECT: u8 = 0b00000100;
pub const ZEROTH_FIRST_OPERANDS_INDIRECT: u8 = ZEROTH_OPERAND_INDIRECT | FIRST_OPERAND_INDIRECT;

/// A simple representation of an AVM instruction for the purpose
Expand Down
92 changes: 87 additions & 5 deletions avm-transpiler/src/transpile.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ use acvm::brillig_vm::brillig::{

use crate::instructions::{
AvmInstruction, AvmOperand, AvmTypeTag, ALL_DIRECT, FIRST_OPERAND_INDIRECT,
ZEROTH_OPERAND_INDIRECT,
SECOND_OPERAND_INDIRECT, ZEROTH_OPERAND_INDIRECT,
};
use crate::opcodes::AvmOpcode;
use crate::utils::{dbg_print_avm_program, dbg_print_brillig_program};
Expand Down Expand Up @@ -256,9 +256,11 @@ fn handle_foreign_call(
}
"avmOpcodePoseidon" => {
handle_single_field_hash_instruction(avm_instrs, function, destinations, inputs)
}
},
"storageRead" => handle_storage_read(avm_instrs, destinations, inputs),
"storageWrite" => handle_storage_write(avm_instrs, destinations, inputs),
// Getters.
_ if inputs.len() == 0 && destinations.len() == 1 => {
_ if inputs.is_empty() && destinations.len() == 1 => {
handle_getter_instruction(avm_instrs, function, destinations, inputs)
}
// Anything else.
Expand Down Expand Up @@ -314,7 +316,7 @@ fn handle_emit_unencrypted_log(
destinations: &Vec<ValueOrArray>,
inputs: &Vec<ValueOrArray>,
) {
if destinations.len() != 0 || inputs.len() != 2 {
if !destinations.is_empty() || inputs.len() != 2 {
panic!(
"Transpiler expects ForeignCall::EMITUNENCRYPTEDLOG to have 0 destinations and 3 inputs, got {} and {}",
destinations.len(),
Expand Down Expand Up @@ -361,7 +363,7 @@ fn handle_emit_note_hash_or_nullifier(
"EMITNOTEHASH"
};

if destinations.len() != 0 || inputs.len() != 1 {
if !destinations.is_empty() || inputs.len() != 1 {
panic!(
"Transpiler expects ForeignCall::{} to have 0 destinations and 1 input, got {} and {}",
function_name,
Expand Down Expand Up @@ -804,6 +806,86 @@ fn handle_black_box_function(avm_instrs: &mut Vec<AvmInstruction>, operation: &B
),
}
}
/// Emit a storage write opcode
/// The current implementation writes an array of values into storage ( contiguous slots in memory )
fn handle_storage_write(
avm_instrs: &mut Vec<AvmInstruction>,
destinations: &Vec<ValueOrArray>,
inputs: &Vec<ValueOrArray>,
) {
assert!(inputs.len() == 2);
assert!(destinations.len() == 1);

let slot_offset_maybe = inputs[0];
let slot_offset = match slot_offset_maybe {
ValueOrArray::MemoryAddress(slot_offset) => slot_offset.0,
_ => panic!("ForeignCall address destination should be a single value"),
};

let src_offset_maybe = inputs[1];
let (src_offset, src_size) = match src_offset_maybe {
ValueOrArray::HeapArray(HeapArray { pointer, size }) => (pointer.0, size),
_ => panic!("Storage write address inputs should be an array of values"),
};

avm_instrs.push(AvmInstruction {
opcode: AvmOpcode::SSTORE,
indirect: Some(ZEROTH_OPERAND_INDIRECT),
operands: vec![
AvmOperand::U32 {
value: src_offset as u32,
},
AvmOperand::U32 {
value: src_size as u32,
},
AvmOperand::U32 {
value: slot_offset as u32,
},
],
..Default::default()
})
}

/// Emit a storage read opcode
/// The current implementation reads an array of values from storage ( contiguous slots in memory )
fn handle_storage_read(
avm_instrs: &mut Vec<AvmInstruction>,
destinations: &Vec<ValueOrArray>,
inputs: &Vec<ValueOrArray>,
) {
// For the foreign calls we want to handle, we do not want inputs, as they are getters
assert!(inputs.len() == 2); // output, len - but we dont use this len - its for the oracle
assert!(destinations.len() == 1);

let slot_offset_maybe = inputs[0];
let slot_offset = match slot_offset_maybe {
ValueOrArray::MemoryAddress(slot_offset) => slot_offset.0,
_ => panic!("ForeignCall address destination should be a single value"),
};

let dest_offset_maybe = destinations[0];
let (dest_offset, src_size) = match dest_offset_maybe {
ValueOrArray::HeapArray(HeapArray { pointer, size }) => (pointer.0, size),
_ => panic!("Storage write address inputs should be an array of values"),
};

avm_instrs.push(AvmInstruction {
opcode: AvmOpcode::SLOAD,
indirect: Some(SECOND_OPERAND_INDIRECT),
operands: vec![
AvmOperand::U32 {
value: slot_offset as u32,
},
AvmOperand::U32 {
value: src_size as u32,
},
AvmOperand::U32 {
value: dest_offset as u32,
},
],
..Default::default()
})
}

/// Compute an array that maps each Brillig pc to an AVM pc.
/// This must be done before transpiling to properly transpile jump destinations.
Expand Down
97 changes: 59 additions & 38 deletions barretenberg/cpp/src/barretenberg/flavor/generated/avm_flavor.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ class AvmFlavor {
static constexpr size_t NUM_ALL_ENTITIES = 91;

using Relations =
std::tuple<Avm_vm::avm_alu<FF>, Avm_vm::avm_main<FF>, Avm_vm::avm_mem<FF>, equiv_inter_reg_alu_relation<FF>>;
std::tuple<Avm_vm::avm_alu<FF>, Avm_vm::avm_mem<FF>, Avm_vm::avm_main<FF>, equiv_inter_reg_alu_relation<FF>>;

@Maddiaa0 Maddiaa0 Mar 7, 2024

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just regenerated these file to get around a conflict, they are just ordering changes ( as codegen is yet to be deterministic )
( nothing to see here ! )


static constexpr size_t MAX_PARTIAL_RELATION_LENGTH = compute_max_partial_relation_length<Relations>();

Expand Down Expand Up @@ -316,20 +316,20 @@ class AvmFlavor {
equiv_inter_reg_alu,
equiv_tag_err,
equiv_tag_err_counts,
avm_alu_alu_u16_r2_shift,
avm_alu_alu_u16_r1_shift,
avm_alu_alu_u16_r6_shift,
avm_alu_alu_u16_r5_shift,
avm_alu_alu_u16_r4_shift,
avm_alu_alu_u16_r0_shift,
avm_alu_alu_u16_r5_shift,
avm_alu_alu_u16_r2_shift,
avm_alu_alu_u16_r7_shift,
avm_alu_alu_u16_r0_shift,
avm_alu_alu_u16_r3_shift,
avm_main_pc_shift,
avm_main_internal_return_ptr_shift,
avm_alu_alu_u16_r6_shift,
avm_alu_alu_u16_r1_shift,
avm_mem_m_val_shift,
avm_mem_m_rw_shift,
avm_mem_m_tag_shift,
avm_mem_m_addr_shift)
avm_mem_m_addr_shift,
avm_main_internal_return_ptr_shift,
avm_main_pc_shift)

RefVector<DataType> get_wires()
{
Expand Down Expand Up @@ -410,20 +410,20 @@ class AvmFlavor {
equiv_inter_reg_alu,
equiv_tag_err,
equiv_tag_err_counts,
avm_alu_alu_u16_r2_shift,
avm_alu_alu_u16_r1_shift,
avm_alu_alu_u16_r6_shift,
avm_alu_alu_u16_r5_shift,
avm_alu_alu_u16_r4_shift,
avm_alu_alu_u16_r0_shift,
avm_alu_alu_u16_r5_shift,
avm_alu_alu_u16_r2_shift,
avm_alu_alu_u16_r7_shift,
avm_alu_alu_u16_r0_shift,
avm_alu_alu_u16_r3_shift,
avm_main_pc_shift,
avm_main_internal_return_ptr_shift,
avm_alu_alu_u16_r6_shift,
avm_alu_alu_u16_r1_shift,
avm_mem_m_val_shift,
avm_mem_m_rw_shift,
avm_mem_m_tag_shift,
avm_mem_m_addr_shift };
avm_mem_m_addr_shift,
avm_main_internal_return_ptr_shift,
avm_main_pc_shift };
};
RefVector<DataType> get_unshifted()
{
Expand Down Expand Up @@ -507,23 +507,37 @@ class AvmFlavor {
};
RefVector<DataType> get_to_be_shifted()
{
return { avm_alu_alu_u16_r2, avm_alu_alu_u16_r1,
avm_alu_alu_u16_r6, avm_alu_alu_u16_r5,
avm_alu_alu_u16_r4, avm_alu_alu_u16_r0,
avm_alu_alu_u16_r7, avm_alu_alu_u16_r3,
avm_main_pc, avm_main_internal_return_ptr,
avm_mem_m_val, avm_mem_m_rw,
avm_mem_m_tag, avm_mem_m_addr };
return { avm_alu_alu_u16_r4,
avm_alu_alu_u16_r5,
avm_alu_alu_u16_r2,
avm_alu_alu_u16_r7,
avm_alu_alu_u16_r0,
avm_alu_alu_u16_r3,
avm_alu_alu_u16_r6,
avm_alu_alu_u16_r1,
avm_mem_m_val,
avm_mem_m_rw,
avm_mem_m_tag,
avm_mem_m_addr,
avm_main_internal_return_ptr,
avm_main_pc };
};
RefVector<DataType> get_shifted()
{
return { avm_alu_alu_u16_r2_shift, avm_alu_alu_u16_r1_shift,
avm_alu_alu_u16_r6_shift, avm_alu_alu_u16_r5_shift,
avm_alu_alu_u16_r4_shift, avm_alu_alu_u16_r0_shift,
avm_alu_alu_u16_r7_shift, avm_alu_alu_u16_r3_shift,
avm_main_pc_shift, avm_main_internal_return_ptr_shift,
avm_mem_m_val_shift, avm_mem_m_rw_shift,
avm_mem_m_tag_shift, avm_mem_m_addr_shift };
return { avm_alu_alu_u16_r4_shift,
avm_alu_alu_u16_r5_shift,
avm_alu_alu_u16_r2_shift,
avm_alu_alu_u16_r7_shift,
avm_alu_alu_u16_r0_shift,
avm_alu_alu_u16_r3_shift,
avm_alu_alu_u16_r6_shift,
avm_alu_alu_u16_r1_shift,
avm_mem_m_val_shift,
avm_mem_m_rw_shift,
avm_mem_m_tag_shift,
avm_mem_m_addr_shift,
avm_main_internal_return_ptr_shift,
avm_main_pc_shift };
};
};

Expand All @@ -536,13 +550,20 @@ class AvmFlavor {

RefVector<DataType> get_to_be_shifted()
{
return { avm_alu_alu_u16_r2, avm_alu_alu_u16_r1,
avm_alu_alu_u16_r6, avm_alu_alu_u16_r5,
avm_alu_alu_u16_r4, avm_alu_alu_u16_r0,
avm_alu_alu_u16_r7, avm_alu_alu_u16_r3,
avm_main_pc, avm_main_internal_return_ptr,
avm_mem_m_val, avm_mem_m_rw,
avm_mem_m_tag, avm_mem_m_addr };
return { avm_alu_alu_u16_r4,
avm_alu_alu_u16_r5,
avm_alu_alu_u16_r2,
avm_alu_alu_u16_r7,
avm_alu_alu_u16_r0,
avm_alu_alu_u16_r3,
avm_alu_alu_u16_r6,
avm_alu_alu_u16_r1,
avm_mem_m_val,
avm_mem_m_rw,
avm_mem_m_tag,
avm_mem_m_addr,
avm_main_internal_return_ptr,
avm_main_pc };
};

// The plookup wires that store plookup read data.
Expand Down
36 changes: 18 additions & 18 deletions ...nberg/cpp/src/barretenberg/proof_system/circuit_builder/generated/avm_circuit_builder.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -98,20 +98,20 @@ template <typename FF> struct AvmFullRow {
FF equiv_inter_reg_alu{};
FF equiv_tag_err{};
FF equiv_tag_err_counts{};
FF avm_alu_alu_u16_r2_shift{};
FF avm_alu_alu_u16_r1_shift{};
FF avm_alu_alu_u16_r6_shift{};
FF avm_alu_alu_u16_r5_shift{};
FF avm_alu_alu_u16_r4_shift{};
FF avm_alu_alu_u16_r0_shift{};
FF avm_alu_alu_u16_r5_shift{};
FF avm_alu_alu_u16_r2_shift{};
FF avm_alu_alu_u16_r7_shift{};
FF avm_alu_alu_u16_r0_shift{};
FF avm_alu_alu_u16_r3_shift{};
FF avm_main_pc_shift{};
FF avm_main_internal_return_ptr_shift{};
FF avm_alu_alu_u16_r6_shift{};
FF avm_alu_alu_u16_r1_shift{};
FF avm_mem_m_val_shift{};
FF avm_mem_m_rw_shift{};
FF avm_mem_m_tag_shift{};
FF avm_mem_m_addr_shift{};
FF avm_main_internal_return_ptr_shift{};
FF avm_main_pc_shift{};
};

class AvmCircuitBuilder {
Expand Down Expand Up @@ -220,20 +220,20 @@ class AvmCircuitBuilder {
polys.equiv_tag_err_counts[i] = rows[i].equiv_tag_err_counts;
}

polys.avm_alu_alu_u16_r2_shift = Polynomial(polys.avm_alu_alu_u16_r2.shifted());
polys.avm_alu_alu_u16_r1_shift = Polynomial(polys.avm_alu_alu_u16_r1.shifted());
polys.avm_alu_alu_u16_r6_shift = Polynomial(polys.avm_alu_alu_u16_r6.shifted());
polys.avm_alu_alu_u16_r5_shift = Polynomial(polys.avm_alu_alu_u16_r5.shifted());
polys.avm_alu_alu_u16_r4_shift = Polynomial(polys.avm_alu_alu_u16_r4.shifted());
polys.avm_alu_alu_u16_r0_shift = Polynomial(polys.avm_alu_alu_u16_r0.shifted());
polys.avm_alu_alu_u16_r5_shift = Polynomial(polys.avm_alu_alu_u16_r5.shifted());
polys.avm_alu_alu_u16_r2_shift = Polynomial(polys.avm_alu_alu_u16_r2.shifted());
polys.avm_alu_alu_u16_r7_shift = Polynomial(polys.avm_alu_alu_u16_r7.shifted());
polys.avm_alu_alu_u16_r0_shift = Polynomial(polys.avm_alu_alu_u16_r0.shifted());
polys.avm_alu_alu_u16_r3_shift = Polynomial(polys.avm_alu_alu_u16_r3.shifted());
polys.avm_main_pc_shift = Polynomial(polys.avm_main_pc.shifted());
polys.avm_main_internal_return_ptr_shift = Polynomial(polys.avm_main_internal_return_ptr.shifted());
polys.avm_alu_alu_u16_r6_shift = Polynomial(polys.avm_alu_alu_u16_r6.shifted());
polys.avm_alu_alu_u16_r1_shift = Polynomial(polys.avm_alu_alu_u16_r1.shifted());
polys.avm_mem_m_val_shift = Polynomial(polys.avm_mem_m_val.shifted());
polys.avm_mem_m_rw_shift = Polynomial(polys.avm_mem_m_rw.shifted());
polys.avm_mem_m_tag_shift = Polynomial(polys.avm_mem_m_tag.shifted());
polys.avm_mem_m_addr_shift = Polynomial(polys.avm_mem_m_addr.shifted());
polys.avm_main_internal_return_ptr_shift = Polynomial(polys.avm_main_internal_return_ptr.shifted());
polys.avm_main_pc_shift = Polynomial(polys.avm_main_pc.shifted());

return polys;
}
Expand Down Expand Up @@ -309,14 +309,14 @@ class AvmCircuitBuilder {
Avm_vm::get_relation_label_avm_alu)) {
return false;
}
if (!evaluate_relation.template operator()<Avm_vm::avm_main<FF>>("avm_main",
Avm_vm::get_relation_label_avm_main)) {
return false;
}
if (!evaluate_relation.template operator()<Avm_vm::avm_mem<FF>>("avm_mem",
Avm_vm::get_relation_label_avm_mem)) {
return false;
}
if (!evaluate_relation.template operator()<Avm_vm::avm_main<FF>>("avm_main",
Avm_vm::get_relation_label_avm_main)) {
return false;
}

if (!evaluate_logderivative.template operator()<equiv_inter_reg_alu_relation<FF>>("equiv_inter_reg_alu")) {
return false;
Expand Down
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