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Update UltraZed-7EV SOM BDF #31

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Update UltraZed-7EV SOM BDF #31

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211 changes: 211 additions & 0 deletions ultrazed_7ev_som/1.4/board.xml
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<board schema_version="2.1" vendor="avnet.com" name="ultrazed_ev_som" display_name="Avnet UltraZed-7EV SOM" url="http://www.ultrazed.org" preset_file="preset.xml">
<images>
<image name="ultrazed_ev_som.jpg" display_name="UltraZed-7EV SOM" sub_type="board">
<description>UltraZed-7EV SOM File Image</description>
</image>
</images>
<compatible_board_revisions>
<revision id="0">1.0</revision>
</compatible_board_revisions>
<file_version>1.4</file_version>
<description>Avnet UltraZed-7EV SOM</description>

<components>
<component name="part0" display_name="Zynq chip on board" type="fpga" part_name="xczu7ev-fbvb900-1-i" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.ultrazed.org">
<description>FPGA part on the board</description>
<interfaces>

<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
</preferred_ips>
</interface>



<interface mode="slave" name="user_sysclk" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="user_sysclk">
<parameters>
<parameter name="frequency" value="300000000"/>
</parameters>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="ddr4" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="CLK_P" physical_port="user_sysclk_p" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="user_sysclk_p"/>
</pin_maps>
</port_map>
<port_map logical_port="CLK_N" physical_port="user_sysclk_n" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="user_sysclk_n"/>
</pin_maps>
</port_map>
</port_maps>
</interface>

<interface mode="master" name="ddr4_sdram" type="xilinx.com:interface:ddr4_rtl:1.0" of_component="ddr4_sdram" preset_proc="ddr4_sdram_preset">
<description>DDR4 board interface, it can use DDR4 controller IP for connection. </description>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="ddr4" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="ACT_N" physical_port="c0_ddr4_act_n" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_act_n"/>
</pin_maps>
</port_map>
<port_map logical_port="ADR" physical_port="c0_ddr4_adr" dir="out" left="16" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_adr0"/>
<pin_map port_index="1" component_pin="c0_ddr4_adr1"/>
<pin_map port_index="2" component_pin="c0_ddr4_adr2"/>
<pin_map port_index="3" component_pin="c0_ddr4_adr3"/>
<pin_map port_index="4" component_pin="c0_ddr4_adr4"/>
<pin_map port_index="5" component_pin="c0_ddr4_adr5"/>
<pin_map port_index="6" component_pin="c0_ddr4_adr6"/>
<pin_map port_index="7" component_pin="c0_ddr4_adr7"/>
<pin_map port_index="8" component_pin="c0_ddr4_adr8"/>
<pin_map port_index="9" component_pin="c0_ddr4_adr9"/>
<pin_map port_index="10" component_pin="c0_ddr4_adr10"/>
<pin_map port_index="11" component_pin="c0_ddr4_adr11"/>
<pin_map port_index="12" component_pin="c0_ddr4_adr12"/>
<pin_map port_index="13" component_pin="c0_ddr4_adr13"/>
<pin_map port_index="14" component_pin="c0_ddr4_adr14"/>
<pin_map port_index="15" component_pin="c0_ddr4_adr15"/>
<pin_map port_index="16" component_pin="c0_ddr4_adr16"/>
</pin_maps>
</port_map>
<port_map logical_port="BA" physical_port="c0_ddr4_ba" dir="out" left="1" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_ba0"/>
<pin_map port_index="1" component_pin="c0_ddr4_ba1"/>
</pin_maps>
</port_map>
<port_map logical_port="BG" physical_port="c0_ddr4_bg" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_bg"/>
</pin_maps>
</port_map>
<port_map logical_port="CK_C" physical_port="c0_ddr4_ck_c" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_ck_c"/>
</pin_maps>
</port_map>
<port_map logical_port="CK_T" physical_port="c0_ddr4_ck_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_ck_t"/>
</pin_maps>
</port_map>
<port_map logical_port="CKE" physical_port="c0_ddr4_cke" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_cke"/>
</pin_maps>
</port_map>
<port_map logical_port="CS_N" physical_port="c0_ddr4_cs_n" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_cs_n"/>
</pin_maps>
</port_map>
<port_map logical_port="DM_N" physical_port="c0_ddr4_dm_dbi_n" dir="inout" left="1" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_dm_dbi_n0"/>
<pin_map port_index="1" component_pin="c0_ddr4_dm_dbi_n1"/>
</pin_maps>
</port_map>
<port_map logical_port="DQ" physical_port="c0_ddr4_dq" dir="inout" left="15" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_dq0"/>
<pin_map port_index="1" component_pin="c0_ddr4_dq1"/>
<pin_map port_index="2" component_pin="c0_ddr4_dq2"/>
<pin_map port_index="3" component_pin="c0_ddr4_dq3"/>
<pin_map port_index="4" component_pin="c0_ddr4_dq4"/>
<pin_map port_index="5" component_pin="c0_ddr4_dq5"/>
<pin_map port_index="6" component_pin="c0_ddr4_dq6"/>
<pin_map port_index="7" component_pin="c0_ddr4_dq7"/>
<pin_map port_index="8" component_pin="c0_ddr4_dq8"/>
<pin_map port_index="9" component_pin="c0_ddr4_dq9"/>
<pin_map port_index="10" component_pin="c0_ddr4_dq10"/>
<pin_map port_index="11" component_pin="c0_ddr4_dq11"/>
<pin_map port_index="12" component_pin="c0_ddr4_dq12"/>
<pin_map port_index="13" component_pin="c0_ddr4_dq13"/>
<pin_map port_index="14" component_pin="c0_ddr4_dq14"/>
<pin_map port_index="15" component_pin="c0_ddr4_dq15"/>
</pin_maps>
</port_map>
<port_map logical_port="DQS_C" physical_port="c0_ddr4_dqs_c" dir="inout" left="1" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_dqs_c0"/>
<pin_map port_index="1" component_pin="c0_ddr4_dqs_c1"/>
</pin_maps>
</port_map>
<port_map logical_port="DQS_T" physical_port="c0_ddr4_dqs_t" dir="out" left="1" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_dqs_t0"/>
<pin_map port_index="1" component_pin="c0_ddr4_dqs_t1"/>
</pin_maps>
</port_map>
<port_map logical_port="ODT" physical_port="c0_ddr4_odt" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_odt"/>
</pin_maps>
</port_map>
<port_map logical_port="RESET_N" physical_port="c0_ddr4_reset_n" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="c0_ddr4_reset_n"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
</interfaces>


</component>
<component name="ps8_fixedio" display_name="PS8 fixed IO" type="chip" sub_type="fixed_io" major_group=""/>


<component name="user_sysclk" display_name="User Differential Clock" type="chip" sub_type="system_clock" major_group="Clock Sources" part_name="SI5341B" vendor="Silicon Labs" spec_url="www.silabs.com">
<description>User Differential 300 MHz Clock. Can be used for DDR4 input system clock</description>
<parameters>
<parameter name="frequency" value="300000000"/>
</parameters>
</component>



<component name="ddr4_sdram" display_name="DDR4 SDRAM" type="chip" sub_type="ddr" major_group="External Memory" part_name="MT40A512M16HA-083E" vendor="Micron" spec_url="https://www.micron.com/parts/dram/ddr4-sdram/mt40a512m16ha-083e">
<description>1GB DDR4 SDRAM memory</description>
<parameters>
<parameter name="ddr_type" value="ddr4"/>
<parameter name="size" value="1GB"/>
</parameters>
</component>
</components>

<jtag_chains>
<jtag_chain name="chain1">
<position name="0" component="part0"/>
</jtag_chain>
</jtag_chains>

<connections>
<connection name="part0_user_sysclk" component1="part0" component2="user_sysclk">
<connection_map name="part0_user_sysclk_1" typical_delay="5" c1_st_index="0" c1_end_index="1" c2_st_index="59" c2_end_index="60"/>
</connection>

</connections>


<ip_associated_rules>
<ip_associated_rule name="default">
<ip vendor="xilinx.com" library="ip" name="ddr4" version="*" ip_interface="C0_SYS_CLK">
<associated_board_interfaces>
<associated_board_interface name="user_sysclk" order="0"/>
</associated_board_interfaces>
</ip>
</ip_associated_rule>
</ip_associated_rules>


</board>
58 changes: 58 additions & 0 deletions ultrazed_7ev_som/1.4/part0_pins.xml
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<part_info part_name="xczu7ev-fbvb900-1-i">
<pins>
<pin index="59" name ="user_sysclk_p" iostandard="DIFF_SSTL12" loc="AC8"/>
<pin index="60" name ="user_sysclk_n" iostandard="DIFF_SSTL12" loc="AC7"/>

<pin index="10" name ="c0_ddr4_act_n" iostandard="SSTL12_DCI" loc="AE2" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="11" name ="c0_ddr4_adr0" iostandard="SSTL12_DCI" loc="AC9" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="12" name ="c0_ddr4_adr1" iostandard="SSTL12_DCI" loc="AD9" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="13" name ="c0_ddr4_adr2" iostandard="SSTL12_DCI" loc="AC6" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="14" name ="c0_ddr4_adr3" iostandard="SSTL12_DCI" loc="AD6" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="15" name ="c0_ddr4_adr4" iostandard="SSTL12_DCI" loc="W8" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="16" name ="c0_ddr4_adr5" iostandard="SSTL12_DCI" loc="Y8" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="17" name ="c0_ddr4_adr6" iostandard="SSTL12_DCI" loc="AA8" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="18" name ="c0_ddr4_adr7" iostandard="SSTL12_DCI" loc="AB8" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="19" name ="c0_ddr4_adr8" iostandard="SSTL12_DCI" loc="W9" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="20" name ="c0_ddr4_adr9" iostandard="SSTL12_DCI" loc="AC12" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="21" name ="c0_ddr4_adr10" iostandard="SSTL12_DCI" loc="AD12" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="22" name ="c0_ddr4_adr11" iostandard="SSTL12_DCI" loc="AA12" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="23" name ="c0_ddr4_adr12" iostandard="SSTL12_DCI" loc="AA11" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="24" name ="c0_ddr4_adr13" iostandard="SSTL12_DCI" loc="AB11" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="25" name ="c0_ddr4_adr14" iostandard="SSTL12_DCI" loc="AC11" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="26" name ="c0_ddr4_adr15" iostandard="SSTL12_DCI" loc="AD11" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="27" name ="c0_ddr4_adr16" iostandard="SSTL12_DCI" loc="AD10" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="28" name ="c0_ddr4_ba0" iostandard="SSTL12_DCI" loc="AB9" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="29" name ="c0_ddr4_ba1" iostandard="SSTL12_DCI" loc="AB10" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="30" name ="c0_ddr4_bg" iostandard="SSTL12_DCI" loc="Y10" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="31" name ="c0_ddr4_ck_c" iostandard="DIFF_SSTL12_DCI" loc="AA7" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="32" name ="c0_ddr4_ck_t" iostandard="DIFF_SSTL12_DCI" loc="Y7" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="33" name ="c0_ddr4_cke" iostandard="SSTL12_DCI" loc="AE7" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="34" name ="c0_ddr4_cs_n" iostandard="SSTL12_DCI" loc="AA10" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="35" name ="c0_ddr4_dm_dbi_n0" iostandard="POD12_DCI" loc="AD2" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="58" name ="c0_ddr4_dm_dbi_n1" iostandard="POD12_DCI" loc="AD7" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="36" name ="c0_ddr4_dq0" iostandard="POD12_DCI" loc="AD1" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="37" name ="c0_ddr4_dq1" iostandard="POD12_DCI" loc="AE1" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="38" name ="c0_ddr4_dq2" iostandard="POD12_DCI" loc="AC3" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="39" name ="c0_ddr4_dq3" iostandard="POD12_DCI" loc="AC2" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="40" name ="c0_ddr4_dq4" iostandard="POD12_DCI" loc="AB1" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="41" name ="c0_ddr4_dq5" iostandard="POD12_DCI" loc="AC1" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="42" name ="c0_ddr4_dq6" iostandard="POD12_DCI" loc="AA2" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="43" name ="c0_ddr4_dq7" iostandard="POD12_DCI" loc="AA1" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="44" name ="c0_ddr4_dq8" iostandard="POD12_DCI" loc="AB6" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="45" name ="c0_ddr4_dq9" iostandard="POD12_DCI" loc="AB5" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="46" name ="c0_ddr4_dq10" iostandard="POD12_DCI" loc="AD5" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="47" name ="c0_ddr4_dq11" iostandard="POD12_DCI" loc="AE5" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="48" name ="c0_ddr4_dq12" iostandard="POD12_DCI" loc="AB4" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="49" name ="c0_ddr4_dq13" iostandard="POD12_DCI" loc="AC4" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="50" name ="c0_ddr4_dq14" iostandard="POD12_DCI" loc="AA6" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="51" name ="c0_ddr4_dq15" iostandard="POD12_DCI" loc="AA5" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="52" name ="c0_ddr4_dqs_c0" iostandard="DIFF_POD12_DCI" loc="AB3" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="53" name ="c0_ddr4_dqs_c1" iostandard="DIFF_POD12_DCI" loc="AE4" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="54" name ="c0_ddr4_dqs_t1" iostandard="DIFF_POD12_DCI" loc="AD4" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="55" name ="c0_ddr4_dqs_t0" iostandard="DIFF_POD12_DCI" loc="AA3" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST" IBUF_LOW_PWR="FALSE" ODT="RTT_40" EQUALIZATION="EQ_LEVEL2" PRE_EMPHASIS="RDRV_240"/>
<pin index="56" name ="c0_ddr4_odt" iostandard="SSTL12_DCI" loc="AE3" OUTPUT_IMPEDANCE="RDRV_40_40" SLEW="FAST"/>
<pin index="57" name ="c0_ddr4_reset_n" iostandard="LVCMOS12" loc="Y1" DRIVE="8"/>

</pins>
</part_info>
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