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Siglent SDS1x0xX-E FPGA bitstreams
Powered by Migen & LiteX
This repo contains a LiteX project for an open source bitstream targetting the Siglent SDS 1x0xX-E series oscilloscopes.
Supported machines:
- Siglent SDS1104X-E or SDS1204X-E (exact same hardware)
Not yet supported (but likely easy to port):
- Siglent SDS1202X-E
- Python3, Vivado WebPACK
- Either a Vivado-compatible JTAG cable (native or XVCD), or OpenOCD.
$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
$ chmod +x litex_setup.py
$ sudo ./litex_setup.py init install
Follow the instructions here to prepare for JTAG boot mode.
$ ./sds1104xe.py --scope-ip=192.168.1.50 --build --load
Instead of --load
(which uses Vivado's hardware manager), configuration with OpenOCD is also possible:
$ openocd -f interface.cfg -f target/zynq_7000.cfg -c "init" -c "zynqpl_program zynq_pl.bs" -c "pld load 0 sds1104xe.bit" -c "exit"
Due to a bug, it may be necessary to re-plug the ethernet cable after the first configuration.
$ litex_server.py --udp --udp-ip 192.168.1.50
Command used to capture a 115.2kbps UART:
$ ./test_adc.py --adc-channels=0 --adc-samples=1000000 --adc-downsampling=256 --afe-range=5.0 --afe-center --plot --dump=dump.csv
Command used to capture 12MHz clk on channel 0 and 6 MHz clk on channel 1:
./test_adc.py --adc-channels=01 --adc-samples=10000 --adc-downsampling=0 --afe-range=5.0 --afe-center --plot --dump=dump.csv
Command used to capture 12MHz clk on channel 0 and push waveforms to GLScopeClient:
./test_scpi.py --control-only
./test_adc.py --adc-channels=0 --adc-samples=16384 --adc-downsampling=0 --afe-range=5.0 --afe-center --glscopeclient
./glscopeclient --debug myscope:aklabs:lan:127.0.0.1
Use ./test_adc.py --help
to get more information about the command line parameters.
Note: Requires
export LC_NUMERIC=en_US.utf-8
with GLScopeClient.