[Bugfix][SM70] Fix decode collapse next to a long chunked prefill (#490)

[areslp]

Purpose

Fixes the decode collapse reported in #490: on SM70 with FLASH_ATTN_V100, a resident long-context sequence decodes at 0.2–0.6 tok/s while another sequence chunk-prefills, and the prefill itself is slower than it would be alone.

Mechanism (measured, not inferred): in a mixed prefill+decode batch FlashAttnV100Impl sends every row through the per-sequence loop of _flash_v100_prefill_with_prefix, so the resident decoder's q=1 row (or an MTP verify row, q = K+1) lands on flash_attn_prefill_paged. That kernel's grid is (ceil(q/BM), 1, B*H), so a single-query row gets one CTA per query head walking the whole context serially: 58 ms per layer at 240K context, 0.93 s per engine step over the 16 full-attention layers, versus 1.8 ms per layer on the paged decode XQA kernel. This is ~85% of the fixed per-step cost the issue observed; the rest is GPU-time sharing with the prefill chunk, which is what the pacing knob addresses.

Three opt-in knobs, all default off, default paths byte-identical:

• VLLM_FLASH_V100_PREFILL_PREFIX_DECODE_ROWS=1 — rows with 1 <= q <= VLLM_FLASH_V100_SMALLQ_DECODE_MAX_Q and prefix context are expanded token-wise (the MTP-verifier expansion) into one paged-decode call; the per-sequence loop skips them.
• VLLM_1CAT_PREFILL_PACE_STEPS=N — while any running request is decoding, a request still in prompt prefill is scheduled a chunk only every N engine steps (Request.next_decode_eligible_step); the other N−1 steps are decode-only.
• VLLM_FLASH_V100_PREFILL_D256_BM32_ANY_PAGE=1 — with MTP the Mamba page gains num_spec conv slots and the align-mode attention block becomes 816 instead of 784, which silently dropped every prefill chunk call off the BM32 phase kernel's page-784-only fast path (2.3x slower). page_block_size becomes a kernel argument and the gate accepts multiples of 16 when set. Page 784 keeps its existing gate and path.

Not changed: the M < 32 low-smem software-pipeline gates and the fp8 bridge workspace still assume page 784.

Test Plan

• pytest tests/kernels/attention/test_sm70_flash_v100_prefix_decode_rows.py — backend-level exactness on a synthetic mixed batch (fp16 and fp8_e5m2 KV, page 16 and 784, rows q=1/5/16): chunk row bit-identical with the flag off/on, small-q rows within fp16 tolerance, route asserted.
• pytest tests/kernels/attention/test_sm70_flash_v100_paged_prefill_any_page.py — pages 816/896 at q=32/784 against page 784 and a dense reference, flag off/on.
• pytest tests/kernels/attention/test_sm70_flash_v100_*.py tests/kernels/attention/test_sm70_e4m3_scalar_fp32.py with each flag off and on.
• End to end on 2x Tesla V100-PCIE-32GB (TP2, --disable-custom-all-reduce), Qwen3.8-27B-QUASAR-NVFP4, --max-model-len 262144 --max-num-seqs 3 --enable-prefix-caching, budget 2048: sequence A resident at 240,000 tokens and decoding, sequence B arriving cold with a 16,384- or 131,072-token prompt; A's rate is measured from B's admission to B's first token, per token (speculative chunks carry several tokens). Fixed prompts, separate server boot per configuration, zero preemptions in every cell.

Test Result

Unit tests: 16/16 and 8/8 pass; the SM70 Flash-V100 suite passes with every flag off and on (147 tests).

fp16 KV, no MTP (A during B's prefill / B prefill time):

config	B = 16K	B = 131K
baseline	0.62 tok/s / 33.9 s	0.50 tok/s / 336.9 s
PREFIX_DECODE_ROWS=1	1.42 tok/s / 14.8 s	0.91 tok/s / 184.1 s

fp16 KV, MTP4 (VLLM_1CAT_ENABLE_SM70_MTP_DEFAULTS=1):

config	B = 16K	B = 131K
baseline	2.57 tok/s / 32.7 s	1.74 tok/s / 412.3 s
PREFIX_DECODE_ROWS=1	4.22 / 21.3 s	2.25 / 314.7 s
+ BM32_ANY_PAGE=1	4.59 / 19.6 s	3.38 / 207.9 s
+ PACE_STEPS=4	11.6 / 30.4 s	9.9 / 293.8 s
+ PACE_STEPS=8 (no any-page)	14.6 / 45.6 s	12.0 / 514.6 s

A's own step count is unchanged by the fix (it removes ~0.9 s from every mixed step); output tokens are identical across boots with the flags off and on, and logprob shifts stay inside the measured cross-boot noise floor. Two sequences decoding together were never the problem (19–27 tok/s after the prefill in every cell).

fp8_e5m2 KV (the issue's configuration):

The issue's exact KV dtype, same harness (attention block 1568, so one 1568-token chunk per step):

config	B = 16K	B = 131K
baseline, no MTP	0.29 tok/s / 35.0 s	0.27 tok/s / 309.1 s
PREFIX_DECODE_ROWS=1	0.71 / 14.1 s	0.56 / 149.9 s
MTP4 baseline	1.30 / 37.0 s	1.14 / 326.2 s
MTP4 + PREFIX_DECODE_ROWS=1 + BM32_ANY_PAGE=1	2.43 / 16.4 s	2.21 / 168.8 s
+ PACE_STEPS=4	8.45 / 20.7 s	6.96 / 203.5 s

The baseline rows reproduce the numbers in the issue thread (0.27 tok/s at a 131K partner, 0.22 at 240K). On fp8 the fix removes ~1.6 s per mixed step, more than on fp16, because the q=1 row was also taking the in-kernel fp8 dequant path of the prefill kernel. B's generated tokens are identical across all fp8 boots; A's greedy tokens diverge at low-confidence positions between any two fp8 boots (including two runs with identical kernels), so token identity is not a usable criterion on fp8. Route accuracy was checked directly instead: for q=1 and q=5 rows at 16K–240K on the same fp8_e5m2 bytes, the old route (prefill_paged, in-kernel dequant) and the new route (decode XQA and scalar) are both within 1.4e-6–6.2e-6 max / ~3e-7–1.2e-6 mean of an fp32 exact reference, i.e. indistinguishable at fp16 output precision.

Standalone kernel timing (q=784 at 104K context, 12/2 heads, fp16): page 784 43.99 ms; pages 800/816/832/896/1008/1568 104.4 ms; with BM32_ANY_PAGE=1 pages 816/896 43.99 ms, bit-identical output.

AI-assisted contribution

The analysis, kernel/backend/scheduler changes and tests were produced with Claude (Anthropic) under my direction; I reviewed every changed line and ran the measurements above on my hardware. Commits carry Co-authored-by trailers.

🤖 Generated with Claude Code

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[Leonccaa]

I replaced my earlier comment because it used the wrong workload for evaluating #616. The relevant test is a mixed phase: two resident long-context requests (A/B, about 170K/175K tokens) are decoding, then a third cold 14,023-token prefill (C) is injected. This directly measures the prefill/decode trade-off.

Test setup: CT252, 4x Tesla V100-PCIE-32GB, Qwen3.8 Flash-Next AWQ, TP4, MTP3, FP16 KV, 493,491-token KV capacity, max_num_batched_tokens=8192. The four arms used the same rebuilt native extension and passed the cache/output audit.

Arm	A decode before C, paired with B (tok/s)	A decode while C prefills (tok/s)	C TTFT	C admission to first token
#616 flags off	69.185	12.736	20.799 s	6.083 s
PREFIX_DECODE_ROWS=1	68.972	12.748	22.491 s	6.706 s
PREFIX_DECODE_ROWS=1 + BM32_ANY_PAGE=1	69.064	12.237	22.477 s	6.903 s
+ PACE_STEPS=4	69.000	29.983	23.048 s	8.704 s

The result is a clear trade-off. In this QSA/Flash-Next workload, the rows and any-page flags did not improve the active decoder by themselves. The pacing knob was the effective part: it raised A's decode rate during C's prefill by about 2.35x versus the all-off control (2.45x versus the rows+any-page arm), while increasing C's TTFT by 2.25 s (+10.8%) and admission-to-first-token by 2.62 s (+43.1%). The normal A+B decode rate before C stayed about 69 tok/s in every arm, so the change protects an existing decode stream during prefill rather than increasing steady-state decode throughput.

This is the evidence I should have reported for #616. It supports the mixed-prefill/decode fix and makes the latency cost explicit; it is separate from the prefix-cache retention issue addressed by #617. Raw logs and the analysis are in staging/ct252-c2-decode-20260912/gpu-validation/ (plus616-*-impact*.log) in our fork.