[Kernel][SM70] Port actual FlashInfer CUDA decode to sparse QSA (prototype)

[yangzhuxinyzx]

Purpose

Begin a real FlashInfer CUDA source port to Volta, starting with sparse QSA.
Instantiate the actual upstream paged-decode and cascade kernels through an
ordered virtual-page adapter; no forwarding to Triton or Flash-V100. This is
an experimental benchmark entry, not a serving/default change.

• Base SHA: 755baae1d075ee04fa9096b23fc0225b23589a86 (main).
• Initial head: 6b2f4ad8e9c1ddebf375bb1ea163dc2b5891ced4.
• FlashInfer: 6c14bbd5ff34210404d5d4b5f6ff3b4b2527f59f, unmodified headers.
• CCCL: 16bd510c9b712e82b0ab6cbb630d8e29ba1f7116.
• No duplicate open FlashInfer PR found. Unlike [Kernel][WIP] Follow up FlashNext batch HC fusion and QSA route audit #504/[Kernel][WIP] Optimize exact single-request Qwen3.8 QSA and router #507, this uses the
  upstream FlashInfer CUDA computation, not another existing native-FA route
  or a changed Triton launch heuristic. Issue [Perf][SM70/SM75] Pre-Ampere tuning findings from a mixed Volta/Turing rig — QSA #441's older prefill dispatch
  fix is already on main and is not repeated here.

Implementation: FP16 D256, variable batch/page/selection width, GQA 1/2/4/6/8,
ordered selections including duplicates, 64-bit KV offsets, invalid-slot zero
loads, FP32 partials/LSE, persistent per-instance buffers and graph-compatible
GPU preparation. Upstream's existing pre-SM80 synchronous-load fallback is
used. The global FlashInfer hardware gate remains unchanged.

Test Plan

• CPU-only native sm_70 compilation and library loading.
• Independent FP32 oracle, repeated indices, invalid rows/pages, empty states,
  strided tensors, alignment guards and poisoned-buffer CUDA Graph replay.
• Paired component timing against the current two-warp Triton route at
  B1/4/8/16, with index preparation and merge included.
• Sanitizer, serving metadata integration and E2E/task-level quality before
  runtime admission. No model speed claim from component or compile results.
• Targets remain C4/C8/C16 = 238/420/728 aggregate no-MTP decode tok/s against
  the fixed 70 tok/s single-request denominator.

Test Result

• Native CUDA 12.8 SM70 compile and load: passed.
• cuobjdump: native sm_70, GQA6 72 registers/thread, zero stack/local.
• CPU pytest: 5 passed, 9 skipped; GPU skips are not GPU passes.
• All applicable staged pre-commit hooks passed (Ruff, CUDA/C++ formatting,
  mypy, shellcheck, Markdown and repository-specific checks).
• GPU pytest: 14 passed, including graph replay and poisoned-buffer cases.
• Compute Sanitizer 12.8.93: 2 targeted cases, memcheck 0 errors;
  racecheck 0 errors / 0 warnings. Older system sanitizer failures were
  not counted as passes; see worklog.
• Paired warmed CUDA Graph microbenchmark, V100-SXM2, local Hq6/Hkv1/D256,
  8192 context / 2051 sparse slots / page784, 11 samples x 100 calls:

Rows	Current Triton us	FlashInfer us	Splits	Latency change
1	27.228	30.556	32	+12.22% regression
4	54.641	45.066	32	-17.52%
8	100.055	60.611	32	-39.42%
16	167.311	87.491	16	-47.71%

The FlashInfer arm includes preparation + decode + merge; best splits are
from an exploratory 16/32/64 sweep. Auto boost, post-sample 1530/877 MHz,
driver 580.173.02. Maximum observed relative L2 versus FP32 = 0.00021144.
No E2E/model-quality acceptance or default change; B1 regression explicitly
prevents global admission. GPU processes exited and memory released.

Commands and contract: docs/design/sm70_flashinfer_qsa_port.md.
The benchmark-only test is run with --confcutdir=flashinfer-sm70/tests; no
new wheel is required. Generated build/test artifacts remain unversioned.

Risks: SIMT may be slower than the existing tensor-core route; numerical
reduction order differs and task quality is not proven by an FP32 unit oracle.
FP8 KV, prefill, fused gate, GDN/conv and TP integration are later stages, not
claimed supported by this prototype. Keep Draft until GPU gates and human
review are complete.

This work is AI-assisted (Codex); human maintainer review is required before
promotion or merge. All commits carry DCO sign-off and AI attribution.