feat: poseidon2 input pack (byte-input-padding-only)
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reshmem
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poseidon2 input packposeidon2 input pack
# Conflicts: # circuits/src/poseidon2_sponge/columns.rs # circuits/src/stark/mozak_stark.rs # runner/src/poseidon2.rs
reshmem
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poseidon2 input packposeidon2 input pack (byte-input-padding-only)
# Conflicts: # circuits/src/stark/mozak_stark.rs
# Conflicts: # circuits/src/stark/mozak_stark.rs
| value: value.preimage[i], | ||
| ..Default::default() | ||
| // each Field element in preimage represents packed data (packed bytes) | ||
| (0..Poseidon2Permutation::<F>::RATE) |
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TODO(Matthias): this is all very suspicious.
Base automatically changed from
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April 13, 2024 06:41
Basically, the bug allows applying sponge permutation on a given chunk of packed field elements in arbitrary order. That is, prover, instead of supplying given chunk c: [F; 8] in the intended order [c_1, c_2 ...c_8]` to Poseidon2Sponge, can instead supply it in any way he wants!
Here is how:
Say prover packs two field elements out of address region (0...14) with content [1, 2 ... 14]
So corresponding packed values would be
let packed_1 = Poseidon2PreimagePack<F> {
pub clk: some_clk,
pub byte_addr: 0,
pub fe_addr: 0,
pub bytes: [1, 2 ..7], // 2261738553347342
pub is_executed: 1,
}
let packed_2 = Poseidon2PreimagePack<F> {
pub clk: some_clk,
pub byte_addr: 8,
pub fe_addr: 1,
pub bytes: [8, 9, .. 14], // 283686952306183
pub is_executed: 1,
}
The idea is that there is no constraint tying byte_addr with fe_addr.
That is, the malicious prover can flip the above fe_addrs by (packed_1.fe_addr, packed_2.fe_addr) = (packed_2.fe_addr, packed_1.fe_addr).
It won't be detected anywhere!
Hence when supplying the above to Poseidon2Sponge, he can emulate that he is supplying 283686952306183 before 2261738553347342.
Simply because the former pack has fe_addr=0, and the latter pack has fe_addr=1 after modification.
So instead of sponge permutation acting on [2261738553347342, 283686952306183...],
it acts on [283686952306183, 2261738553347342...], hence leading to different output.
In the former codebase, this can't happen because of CTL against Memory stark, which ensures that input to Poseidon2Sponge is coming in correct order (according to their addresses). But in the current implementation, there is no restriction, because fe_addr is not a real address as you pointed out!
I think there is an easy way out though. We change the interpretation of input_addr in Poseidon2Sponge
pub struct Poseidon2Sponge<T> {
pub clk: T,
pub ops: Ops<T>,
pub input_addr: T,
pub output_addr: T,
pub input_len: T,
pub preimage: [T; WIDTH],
pub output: [T; WIDTH],
pub gen_output: T,
pub input_addr_padded: T,
}
Earlier this said "Hey, I am taking 8 bytes in region input_addr...input_addr+8, feeding it to current sponge preimage , apply sponge permutation, and I get output . I have also ordered the trace in increasing order of input_addr which you can check. Hence, you can be sure I am feeding it in correct order."
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Would recomment @codeblooded1729 to take a look. Although part of SDK, this was last touched (and mostly coded up by @codeblooded1729). Not many touch-points here for me! |
# Conflicts: # circuits/src/generation/mod.rs # circuits/src/stark/mozak_stark.rs # sdk/Cargo.toml
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poseidon2-preimage-packtomemoryposeidon2-spongetoposeidon2-preimage-pack+reduce_with_powersto make 1 field element out of 7 bytesMe and @codeblooded1729 think that this implementation will be performant especially in case of data-input length more than 256 bytes.
For small input, like 32 bytes performance can be decreased .
Benchmarking shows 15-20% increase in performance overall. For very small input, the results are very noisy since
poseidon2is part ofmozak-starkand its run-time is less than other starks.