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@@ -562,3 +562,13 @@ Description: Umwait control | |
or C0.2 state. The time is an unsigned 32-bit number. | ||
Note that a value of zero means there is no limit. | ||
Low order two bits must be zero. | ||
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What: /sys/devices/system/cpu/svm | ||
Date: August 2019 | ||
Contact: Linux kernel mailing list <[email protected]> | ||
Linux for PowerPC mailing list <[email protected]> | ||
Description: Secure Virtual Machine | ||
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If 1, it means the system is using the Protected Execution | ||
Facility in POWER9 and newer processors. i.e., it is a Secure | ||
Virtual Machine. |
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22 changes: 22 additions & 0 deletions
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Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
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Mediatek ipesys controller | ||
============================ | ||
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The Mediatek ipesys controller provides various clocks to the system. | ||
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Required Properties: | ||
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- compatible: Should be one of: | ||
- "mediatek,mt6779-ipesys", "syscon" | ||
- #clock-cells: Must be 1 | ||
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The ipesys controller uses the common clk binding from | ||
Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
The available clocks are defined in dt-bindings/clock/mt*-clk.h. | ||
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Example: | ||
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ipesys: clock-controller@1b000000 { | ||
compatible = "mediatek,mt6779-ipesys", "syscon"; | ||
reg = <0 0x1b000000 0 0x1000>; | ||
#clock-cells = <1>; | ||
}; |
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60
Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt
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* Rockchip RK3308 Clock and Reset Unit | ||
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The RK3308 clock controller generates and supplies clock to various | ||
controllers within the SoC and also implements a reset controller for SoC | ||
peripherals. | ||
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Required Properties: | ||
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- compatible: CRU should be "rockchip,rk3308-cru" | ||
- reg: physical base address of the controller and length of memory mapped | ||
region. | ||
- #clock-cells: should be 1. | ||
- #reset-cells: should be 1. | ||
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Optional Properties: | ||
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- rockchip,grf: phandle to the syscon managing the "general register files" | ||
If missing, pll rates are not changeable, due to the missing pll lock status. | ||
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Each clock is assigned an identifier and client nodes can use this identifier | ||
to specify the clock which they consume. All available clocks are defined as | ||
preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be | ||
used in device tree sources. Similar macros exist for the reset sources in | ||
these files. | ||
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External clocks: | ||
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There are several clocks that are generated outside the SoC. It is expected | ||
that they are defined using standard clock bindings with following | ||
clock-output-names: | ||
- "xin24m" - crystal input - required, | ||
- "xin32k" - rtc clock - optional, | ||
- "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in", | ||
"mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in", | ||
"mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional, | ||
- "mac_clkin" - external MAC clock - optional | ||
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Example: Clock controller node: | ||
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cru: clock-controller@ff500000 { | ||
compatible = "rockchip,rk3308-cru"; | ||
reg = <0x0 0xff500000 0x0 0x1000>; | ||
rockchip,grf = <&grf>; | ||
#clock-cells = <1>; | ||
#reset-cells = <1>; | ||
}; | ||
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Example: UART controller node that consumes the clock generated by the clock | ||
controller: | ||
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uart0: serial@ff0a0000 { | ||
compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; | ||
reg = <0x0 0xff0a0000 0x0 0x100>; | ||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | ||
clock-names = "baudclk", "apb_pclk"; | ||
reg-shift = <2>; | ||
reg-io-width = <4>; | ||
status = "disabled"; | ||
}; |
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