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llvm.zig
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const std = @import("std");
const builtin = @import("builtin");
const assert = std.debug.assert;
const Allocator = std.mem.Allocator;
const log = std.log.scoped(.codegen);
const math = std.math;
const DW = std.dwarf;
const Builder = @import("llvm/Builder.zig");
const llvm = if (build_options.have_llvm)
@import("llvm/bindings.zig")
else
@compileError("LLVM unavailable");
const link = @import("../link.zig");
const Compilation = @import("../Compilation.zig");
const build_options = @import("build_options");
const Zcu = @import("../Zcu.zig");
const InternPool = @import("../InternPool.zig");
const Package = @import("../Package.zig");
const Air = @import("../Air.zig");
const Liveness = @import("../Liveness.zig");
const Value = @import("../Value.zig");
const Type = @import("../Type.zig");
const x86_64_abi = @import("../arch/x86_64/abi.zig");
const wasm_c_abi = @import("../arch/wasm/abi.zig");
const aarch64_c_abi = @import("../arch/aarch64/abi.zig");
const arm_c_abi = @import("../arch/arm/abi.zig");
const riscv_c_abi = @import("../arch/riscv64/abi.zig");
const mips_c_abi = @import("../arch/mips/abi.zig");
const dev = @import("../dev.zig");
const target_util = @import("../target.zig");
const libcFloatPrefix = target_util.libcFloatPrefix;
const libcFloatSuffix = target_util.libcFloatSuffix;
const compilerRtFloatAbbrev = target_util.compilerRtFloatAbbrev;
const compilerRtIntAbbrev = target_util.compilerRtIntAbbrev;
const Error = error{ OutOfMemory, CodegenFail };
fn subArchName(features: std.Target.Cpu.Feature.Set, arch: anytype, mappings: anytype) ?[]const u8 {
inline for (mappings) |mapping| {
if (arch.featureSetHas(features, mapping[0])) return mapping[1];
}
return null;
}
pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
var llvm_triple = std.ArrayList(u8).init(allocator);
defer llvm_triple.deinit();
const features = target.cpu.features;
const llvm_arch = switch (target.cpu.arch) {
.arm => "arm",
.armeb => "armeb",
.aarch64 => if (target.abi == .ilp32) "aarch64_32" else "aarch64",
.aarch64_be => "aarch64_be",
.arc => "arc",
.avr => "avr",
.bpfel => "bpfel",
.bpfeb => "bpfeb",
.csky => "csky",
.hexagon => "hexagon",
.loongarch32 => "loongarch32",
.loongarch64 => "loongarch64",
.m68k => "m68k",
// MIPS sub-architectures are a bit irregular, so we handle them manually here.
.mips => if (std.Target.mips.featureSetHas(features, .mips32r6)) "mipsisa32r6" else "mips",
.mipsel => if (std.Target.mips.featureSetHas(features, .mips32r6)) "mipsisa32r6el" else "mipsel",
.mips64 => if (std.Target.mips.featureSetHas(features, .mips64r6)) "mipsisa64r6" else "mips64",
.mips64el => if (std.Target.mips.featureSetHas(features, .mips64r6)) "mipsisa64r6el" else "mips64el",
.msp430 => "msp430",
.powerpc => "powerpc",
.powerpcle => "powerpcle",
.powerpc64 => "powerpc64",
.powerpc64le => "powerpc64le",
.amdgcn => "amdgcn",
.riscv32 => "riscv32",
.riscv64 => "riscv64",
.sparc => "sparc",
.sparc64 => "sparc64",
.s390x => "s390x",
.thumb => "thumb",
.thumbeb => "thumbeb",
.x86 => "i386",
.x86_64 => "x86_64",
.xcore => "xcore",
.xtensa => "xtensa",
.nvptx => "nvptx",
.nvptx64 => "nvptx64",
.spirv => "spirv",
.spirv32 => "spirv32",
.spirv64 => "spirv64",
.lanai => "lanai",
.wasm32 => "wasm32",
.wasm64 => "wasm64",
.ve => "ve",
.kalimba,
.spu_2,
.propeller1,
.propeller2,
=> unreachable, // Gated by hasLlvmSupport().
};
try llvm_triple.appendSlice(llvm_arch);
const llvm_sub_arch: ?[]const u8 = switch (target.cpu.arch) {
.arm, .armeb, .thumb, .thumbeb => subArchName(features, std.Target.arm, .{
.{ .v4t, "v4t" },
.{ .v5t, "v5t" },
.{ .v5te, "v5te" },
.{ .v5tej, "v5tej" },
.{ .v6, "v6" },
.{ .v6k, "v6k" },
.{ .v6kz, "v6kz" },
.{ .v6m, "v6m" },
.{ .v6t2, "v6t2" },
.{ .v7a, "v7a" },
.{ .v7em, "v7em" },
.{ .v7m, "v7m" },
.{ .v7r, "v7r" },
.{ .v7ve, "v7ve" },
.{ .v8a, "v8a" },
.{ .v8_1a, "v8.1a" },
.{ .v8_2a, "v8.2a" },
.{ .v8_3a, "v8.3a" },
.{ .v8_4a, "v8.4a" },
.{ .v8_5a, "v8.5a" },
.{ .v8_6a, "v8.6a" },
.{ .v8_7a, "v8.7a" },
.{ .v8_8a, "v8.8a" },
.{ .v8_9a, "v8.9a" },
.{ .v8m, "v8m.base" },
.{ .v8m_main, "v8m.main" },
.{ .v8_1m_main, "v8.1m.main" },
.{ .v8r, "v8r" },
.{ .v9a, "v9a" },
.{ .v9_1a, "v9.1a" },
.{ .v9_2a, "v9.2a" },
.{ .v9_3a, "v9.3a" },
.{ .v9_4a, "v9.4a" },
.{ .v9_5a, "v9.5a" },
}),
.powerpc => subArchName(features, std.Target.powerpc, .{
.{ .spe, "spe" },
}),
.spirv => subArchName(features, std.Target.spirv, .{
.{ .v1_5, "1.5" },
}),
.spirv32, .spirv64 => subArchName(features, std.Target.spirv, .{
.{ .v1_5, "1.5" },
.{ .v1_4, "1.4" },
.{ .v1_3, "1.3" },
.{ .v1_2, "1.2" },
.{ .v1_1, "1.1" },
}),
else => null,
};
if (llvm_sub_arch) |sub| try llvm_triple.appendSlice(sub);
try llvm_triple.append('-');
try llvm_triple.appendSlice(switch (target.os.tag) {
.aix,
.zos,
=> "ibm",
.bridgeos,
.driverkit,
.ios,
.macos,
.tvos,
.visionos,
.watchos,
=> "apple",
.ps4,
.ps5,
=> "scei",
.amdhsa,
.amdpal,
=> "amd",
.cuda,
.nvcl,
=> "nvidia",
.mesa3d,
=> "mesa",
else => "unknown",
});
try llvm_triple.append('-');
const llvm_os = switch (target.os.tag) {
.freestanding => "unknown",
.dragonfly => "dragonfly",
.freebsd => "freebsd",
.fuchsia => "fuchsia",
.linux => "linux",
.ps3 => "lv2",
.netbsd => "netbsd",
.openbsd => "openbsd",
.solaris, .illumos => "solaris",
.windows, .uefi => "windows",
.zos => "zos",
.haiku => "haiku",
.rtems => "rtems",
.aix => "aix",
.cuda => "cuda",
.nvcl => "nvcl",
.amdhsa => "amdhsa",
.opencl => "unknown", // https://llvm.org/docs/SPIRVUsage.html#target-triples
.ps4 => "ps4",
.ps5 => "ps5",
.elfiamcu => "elfiamcu",
.mesa3d => "mesa3d",
.amdpal => "amdpal",
.hermit => "hermit",
.hurd => "hurd",
.wasi => "wasi",
.emscripten => "emscripten",
.bridgeos => "bridgeos",
.macos => "macosx",
.ios => "ios",
.tvos => "tvos",
.watchos => "watchos",
.driverkit => "driverkit",
.visionos => "xros",
.serenity => "serenity",
.vulkan => "vulkan",
.opengl,
.plan9,
.contiki,
.other,
=> "unknown",
};
try llvm_triple.appendSlice(llvm_os);
switch (target.os.versionRange()) {
.none,
.windows,
=> {},
.semver => |ver| try llvm_triple.writer().print("{d}.{d}.{d}", .{
ver.min.major,
ver.min.minor,
ver.min.patch,
}),
.linux => |ver| try llvm_triple.writer().print("{d}.{d}.{d}", .{
ver.range.min.major,
ver.range.min.minor,
ver.range.min.patch,
}),
}
try llvm_triple.append('-');
const llvm_abi = switch (target.abi) {
.none, .ilp32 => "unknown",
.gnu => "gnu",
.gnuabin32 => "gnuabin32",
.gnuabi64 => "gnuabi64",
.gnueabi => "gnueabi",
.gnueabihf => "gnueabihf",
.gnuf32 => "gnuf32",
.gnusf => "gnusf",
.gnux32 => "gnux32",
.gnuilp32 => "gnu_ilp32",
.code16 => "code16",
.eabi => "eabi",
.eabihf => "eabihf",
.android => "android",
.androideabi => "androideabi",
.musl => "musl",
.muslabin32 => "musl", // Should be muslabin32 in LLVM 20.
.muslabi64 => "musl", // Should be muslabi64 in LLVM 20.
.musleabi => "musleabi",
.musleabihf => "musleabihf",
.muslx32 => "muslx32",
.msvc => "msvc",
.itanium => "itanium",
.cygnus => "cygnus",
.simulator => "simulator",
.macabi => "macabi",
.ohos => "ohos",
.ohoseabi => "ohoseabi",
};
try llvm_triple.appendSlice(llvm_abi);
switch (target.os.versionRange()) {
.none,
.semver,
.windows,
=> {},
.linux => |ver| if (target.abi.isGnu()) try llvm_triple.writer().print("{d}.{d}.{d}", .{
ver.glibc.major,
ver.glibc.minor,
ver.glibc.patch,
}) else if (target.abi.isAndroid()) try llvm_triple.writer().print("{d}", .{ver.android}),
}
return llvm_triple.toOwnedSlice();
}
pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType {
return switch (os_tag) {
.freestanding => .UnknownOS,
.windows, .uefi => .Win32,
.dragonfly => .DragonFly,
.freebsd => .FreeBSD,
.fuchsia => .Fuchsia,
.ios => .IOS,
.linux => .Linux,
.ps3 => .Lv2,
.macos => .MacOSX,
.netbsd => .NetBSD,
.openbsd => .OpenBSD,
.solaris, .illumos => .Solaris,
.zos => .ZOS,
.haiku => .Haiku,
.rtems => .RTEMS,
.aix => .AIX,
.cuda => .CUDA,
.nvcl => .NVCL,
.amdhsa => .AMDHSA,
.opencl => .UnknownOS, // https://llvm.org/docs/SPIRVUsage.html#target-triples
.ps4 => .PS4,
.ps5 => .PS5,
.elfiamcu => .ELFIAMCU,
.tvos => .TvOS,
.watchos => .WatchOS,
.visionos => .XROS,
.mesa3d => .Mesa3D,
.amdpal => .AMDPAL,
.hermit => .HermitCore,
.hurd => .Hurd,
.wasi => .WASI,
.emscripten => .Emscripten,
.driverkit => .DriverKit,
.vulkan => .Vulkan,
.serenity => .Serenity,
.bridgeos => .BridgeOS,
.opengl,
.plan9,
.contiki,
.other,
=> .UnknownOS,
};
}
pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
return switch (arch_tag) {
.arm => .arm,
.armeb => .armeb,
.aarch64 => .aarch64,
.aarch64_be => .aarch64_be,
.arc => .arc,
.avr => .avr,
.bpfel => .bpfel,
.bpfeb => .bpfeb,
.csky => .csky,
.hexagon => .hexagon,
.loongarch32 => .loongarch32,
.loongarch64 => .loongarch64,
.m68k => .m68k,
.mips => .mips,
.mipsel => .mipsel,
.mips64 => .mips64,
.mips64el => .mips64el,
.msp430 => .msp430,
.powerpc => .ppc,
.powerpcle => .ppcle,
.powerpc64 => .ppc64,
.powerpc64le => .ppc64le,
.amdgcn => .amdgcn,
.riscv32 => .riscv32,
.riscv64 => .riscv64,
.sparc => .sparc,
.sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.
.s390x => .systemz,
.thumb => .thumb,
.thumbeb => .thumbeb,
.x86 => .x86,
.x86_64 => .x86_64,
.xcore => .xcore,
.xtensa => .xtensa,
.nvptx => .nvptx,
.nvptx64 => .nvptx64,
.spirv => .spirv,
.spirv32 => .spirv32,
.spirv64 => .spirv64,
.kalimba => .kalimba,
.lanai => .lanai,
.wasm32 => .wasm32,
.wasm64 => .wasm64,
.ve => .ve,
.propeller1, .propeller2, .spu_2 => .UnknownArch,
};
}
pub fn supportsTailCall(target: std.Target) bool {
switch (target.cpu.arch) {
.wasm32, .wasm64 => return std.Target.wasm.featureSetHas(target.cpu.features, .tail_call),
// Although these ISAs support tail calls, LLVM does not support tail calls on them.
.mips, .mipsel, .mips64, .mips64el => return false,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => return false,
else => return true,
}
}
const DataLayoutBuilder = struct {
target: std.Target,
pub fn format(
self: DataLayoutBuilder,
comptime _: []const u8,
_: std.fmt.FormatOptions,
writer: anytype,
) @TypeOf(writer).Error!void {
try writer.writeByte(switch (self.target.cpu.arch.endian()) {
.little => 'e',
.big => 'E',
});
switch (self.target.cpu.arch) {
.amdgcn,
.nvptx,
.nvptx64,
=> {},
.avr => try writer.writeAll("-P1"),
else => try writer.print("-m:{c}", .{@as(u8, switch (self.target.cpu.arch) {
.mips, .mipsel => 'm', // Mips mangling: Private symbols get a $ prefix.
else => switch (self.target.ofmt) {
.elf => 'e', // ELF mangling: Private symbols get a `.L` prefix.
//.goff => 'l', // GOFF mangling: Private symbols get a `@` prefix.
.macho => 'o', // Mach-O mangling: Private symbols get `L` prefix.
// Other symbols get a `_` prefix.
.coff => switch (self.target.os.tag) {
.uefi, .windows => switch (self.target.cpu.arch) {
.x86 => 'x', // Windows x86 COFF mangling: Private symbols get the usual
// prefix. Regular C symbols get a `_` prefix. Functions with `__stdcall`,
//`__fastcall`, and `__vectorcall` have custom mangling that appends `@N`
// where N is the number of bytes used to pass parameters. C++ symbols
// starting with `?` are not mangled in any way.
else => 'w', // Windows COFF mangling: Similar to x, except that normal C
// symbols do not receive a `_` prefix.
},
else => 'e',
},
//.xcoff => 'a', // XCOFF mangling: Private symbols get a `L..` prefix.
else => 'e',
},
})}),
}
const stack_abi = self.target.stackAlignment() * 8;
if (self.target.cpu.arch == .csky) try writer.print("-S{d}", .{stack_abi});
var any_non_integral = false;
const ptr_bit_width = self.target.ptrBitWidth();
var default_info = struct { size: u16, abi: u16, pref: u16, idx: u16 }{
.size = 64,
.abi = 64,
.pref = 64,
.idx = 64,
};
const addr_space_info = llvmAddrSpaceInfo(self.target);
for (addr_space_info, 0..) |info, i| {
assert((info.llvm == .default) == (i == 0));
if (info.non_integral) {
assert(info.llvm != .default);
any_non_integral = true;
}
const size = info.size orelse ptr_bit_width;
const abi = info.abi orelse ptr_bit_width;
const pref = info.pref orelse abi;
const idx = info.idx orelse size;
const matches_default =
size == default_info.size and
abi == default_info.abi and
pref == default_info.pref and
idx == default_info.idx;
if (info.llvm == .default) default_info = .{
.size = size,
.abi = abi,
.pref = pref,
.idx = idx,
};
if (!info.force_in_data_layout and matches_default and
self.target.cpu.arch != .riscv64 and
self.target.cpu.arch != .loongarch64 and
!(self.target.cpu.arch == .aarch64 and
(self.target.os.tag == .uefi or self.target.os.tag == .windows)) and
self.target.cpu.arch != .bpfeb and self.target.cpu.arch != .bpfel) continue;
try writer.writeAll("-p");
if (info.llvm != .default) try writer.print("{d}", .{@intFromEnum(info.llvm)});
try writer.print(":{d}:{d}", .{ size, abi });
if (pref != abi or idx != size or self.target.cpu.arch == .hexagon) {
try writer.print(":{d}", .{pref});
if (idx != size) try writer.print(":{d}", .{idx});
}
}
if (self.target.cpu.arch.isArm())
try writer.writeAll("-Fi8") // for thumb interwork
else if (self.target.cpu.arch == .powerpc64 and
self.target.os.tag != .freebsd and
self.target.os.tag != .openbsd and
!self.target.abi.isMusl())
try writer.writeAll("-Fi64")
else if (self.target.cpu.arch.isPowerPC() and self.target.os.tag == .aix)
try writer.writeAll(if (self.target.cpu.arch.isPowerPC64()) "-Fi64" else "-Fi32")
else if (self.target.cpu.arch.isPowerPC())
try writer.writeAll("-Fn32");
if (self.target.cpu.arch != .hexagon) {
if (self.target.cpu.arch == .arc or self.target.cpu.arch == .s390x)
try self.typeAlignment(.integer, 1, 8, 8, false, writer);
try self.typeAlignment(.integer, 8, 8, 8, false, writer);
try self.typeAlignment(.integer, 16, 16, 16, false, writer);
try self.typeAlignment(.integer, 32, 32, 32, false, writer);
if (self.target.cpu.arch == .arc)
try self.typeAlignment(.float, 32, 32, 32, false, writer);
try self.typeAlignment(.integer, 64, 32, 64, false, writer);
try self.typeAlignment(.integer, 128, 32, 64, false, writer);
if (backendSupportsF16(self.target))
try self.typeAlignment(.float, 16, 16, 16, false, writer);
if (self.target.cpu.arch != .arc)
try self.typeAlignment(.float, 32, 32, 32, false, writer);
try self.typeAlignment(.float, 64, 64, 64, false, writer);
if (self.target.cpu.arch.isX86()) try self.typeAlignment(.float, 80, 0, 0, false, writer);
try self.typeAlignment(.float, 128, 128, 128, false, writer);
}
switch (self.target.cpu.arch) {
.amdgcn => {
try self.typeAlignment(.vector, 16, 16, 16, false, writer);
try self.typeAlignment(.vector, 24, 32, 32, false, writer);
try self.typeAlignment(.vector, 32, 32, 32, false, writer);
try self.typeAlignment(.vector, 48, 64, 64, false, writer);
try self.typeAlignment(.vector, 96, 128, 128, false, writer);
try self.typeAlignment(.vector, 192, 256, 256, false, writer);
try self.typeAlignment(.vector, 256, 256, 256, false, writer);
try self.typeAlignment(.vector, 512, 512, 512, false, writer);
try self.typeAlignment(.vector, 1024, 1024, 1024, false, writer);
try self.typeAlignment(.vector, 2048, 2048, 2048, false, writer);
},
.ve => {},
else => {
try self.typeAlignment(.vector, 16, 32, 32, false, writer);
try self.typeAlignment(.vector, 32, 32, 32, false, writer);
try self.typeAlignment(.vector, 64, 64, 64, false, writer);
try self.typeAlignment(.vector, 128, 128, 128, true, writer);
},
}
const swap_agg_nat = switch (self.target.cpu.arch) {
.x86, .x86_64 => switch (self.target.os.tag) {
.uefi, .windows => true,
else => false,
},
.avr, .m68k => true,
else => false,
};
if (!swap_agg_nat) try self.typeAlignment(.aggregate, 0, 0, 64, false, writer);
if (self.target.cpu.arch == .csky) try writer.writeAll("-Fi32");
for (@as([]const u24, switch (self.target.cpu.arch) {
.avr => &.{8},
.msp430 => &.{ 8, 16 },
.arc,
.arm,
.armeb,
.csky,
.loongarch32,
.mips,
.mipsel,
.powerpc,
.powerpcle,
.riscv32,
.sparc,
.thumb,
.thumbeb,
.xtensa,
=> &.{32},
.aarch64,
.aarch64_be,
.amdgcn,
.bpfeb,
.bpfel,
.loongarch64,
.mips64,
.mips64el,
.powerpc64,
.powerpc64le,
.riscv64,
.s390x,
.sparc64,
.ve,
.wasm32,
.wasm64,
=> &.{ 32, 64 },
.hexagon => &.{ 16, 32 },
.m68k,
.x86,
=> &.{ 8, 16, 32 },
.nvptx,
.nvptx64,
=> &.{ 16, 32, 64 },
.x86_64 => &.{ 8, 16, 32, 64 },
else => &.{},
}), 0..) |natural, index| switch (index) {
0 => try writer.print("-n{d}", .{natural}),
else => try writer.print(":{d}", .{natural}),
};
if (swap_agg_nat) try self.typeAlignment(.aggregate, 0, 0, 64, false, writer);
if (self.target.cpu.arch == .hexagon) {
try self.typeAlignment(.integer, 64, 64, 64, true, writer);
try self.typeAlignment(.integer, 32, 32, 32, true, writer);
try self.typeAlignment(.integer, 16, 16, 16, true, writer);
try self.typeAlignment(.integer, 1, 8, 8, true, writer);
try self.typeAlignment(.float, 32, 32, 32, true, writer);
try self.typeAlignment(.float, 64, 64, 64, true, writer);
}
if (stack_abi != ptr_bit_width or self.target.cpu.arch == .msp430 or
self.target.os.tag == .uefi or self.target.os.tag == .windows or
self.target.cpu.arch == .riscv32)
try writer.print("-S{d}", .{stack_abi});
if (self.target.cpu.arch.isAARCH64())
try writer.writeAll("-Fn32");
switch (self.target.cpu.arch) {
.hexagon, .ve => {
try self.typeAlignment(.vector, 32, 128, 128, true, writer);
try self.typeAlignment(.vector, 64, 128, 128, true, writer);
try self.typeAlignment(.vector, 128, 128, 128, true, writer);
},
else => {},
}
if (self.target.cpu.arch != .amdgcn) {
try self.typeAlignment(.vector, 256, 128, 128, true, writer);
try self.typeAlignment(.vector, 512, 128, 128, true, writer);
try self.typeAlignment(.vector, 1024, 128, 128, true, writer);
try self.typeAlignment(.vector, 2048, 128, 128, true, writer);
try self.typeAlignment(.vector, 4096, 128, 128, true, writer);
try self.typeAlignment(.vector, 8192, 128, 128, true, writer);
try self.typeAlignment(.vector, 16384, 128, 128, true, writer);
}
const alloca_addr_space = llvmAllocaAddressSpace(self.target);
if (alloca_addr_space != .default) try writer.print("-A{d}", .{@intFromEnum(alloca_addr_space)});
const global_addr_space = llvmDefaultGlobalAddressSpace(self.target);
if (global_addr_space != .default) try writer.print("-G{d}", .{@intFromEnum(global_addr_space)});
if (any_non_integral) {
try writer.writeAll("-ni");
for (addr_space_info) |info| if (info.non_integral)
try writer.print(":{d}", .{@intFromEnum(info.llvm)});
}
}
fn typeAlignment(
self: DataLayoutBuilder,
kind: enum { integer, vector, float, aggregate },
size: u24,
default_abi: u24,
default_pref: u24,
default_force_pref: bool,
writer: anytype,
) @TypeOf(writer).Error!void {
var abi = default_abi;
var pref = default_pref;
var force_abi = false;
var force_pref = default_force_pref;
if (kind == .float and size == 80) {
abi = 128;
pref = 128;
}
for (@as([]const std.Target.CType, switch (kind) {
.integer => &.{ .char, .short, .int, .long, .longlong },
.float => &.{ .float, .double, .longdouble },
.vector, .aggregate => &.{},
})) |cty| {
if (self.target.cTypeBitSize(cty) != size) continue;
abi = self.target.cTypeAlignment(cty) * 8;
pref = self.target.cTypePreferredAlignment(cty) * 8;
break;
}
switch (kind) {
.integer => {
if (self.target.ptrBitWidth() <= 16 and size >= 128) return;
abi = @min(abi, Type.maxIntAlignment(self.target, true) * 8);
switch (self.target.cpu.arch) {
.aarch64,
.aarch64_be,
=> if (size == 128) {
abi = size;
pref = size;
} else switch (self.target.os.tag) {
.macos, .ios, .watchos, .tvos, .visionos => {},
.uefi, .windows => {
pref = size;
force_abi = size >= 32;
},
else => pref = @max(pref, 32),
},
.arc => if (size <= 64) {
abi = @min((std.math.divCeil(u24, size, 8) catch unreachable) * 8, 32);
pref = 32;
force_abi = true;
force_pref = size <= 32;
},
.bpfeb,
.bpfel,
.nvptx,
.nvptx64,
.riscv64,
=> if (size == 128) {
abi = size;
pref = size;
},
.csky => if (size == 32 or size == 64) {
abi = 32;
pref = 32;
force_abi = true;
force_pref = true;
},
.hexagon => force_abi = true,
.m68k => if (size <= 32) {
abi = @min(size, 16);
pref = size;
force_abi = true;
force_pref = true;
} else if (size == 64) {
abi = 32;
pref = size;
},
.mips,
.mipsel,
.mips64,
.mips64el,
=> pref = @max(pref, 32),
.s390x => pref = @max(pref, 16),
.ve => if (size == 64) {
abi = size;
pref = size;
},
.xtensa => if (size <= 64) {
pref = @max(size, 32);
abi = size;
force_abi = size == 64;
},
.x86 => switch (size) {
128 => {
abi = size;
pref = size;
},
else => {},
},
.x86_64 => switch (size) {
64, 128 => {
abi = size;
pref = size;
},
else => {},
},
.loongarch64 => switch (size) {
128 => {
abi = size;
pref = size;
force_abi = true;
},
else => {},
},
else => {},
}
},
.vector => if (self.target.cpu.arch.isArm()) {
switch (size) {
128 => abi = 64,
else => {},
}
} else if ((self.target.cpu.arch.isPowerPC64() and self.target.os.tag == .linux and
(size == 256 or size == 512)) or
(self.target.cpu.arch.isNvptx() and (size == 16 or size == 32)))
{
force_abi = true;
abi = size;
pref = size;
} else if (self.target.cpu.arch == .amdgcn and size <= 2048) {
force_abi = true;
} else if (self.target.cpu.arch == .csky and (size == 64 or size == 128)) {
abi = 32;
pref = 32;
force_pref = true;
} else if (self.target.cpu.arch == .hexagon and
((size >= 32 and size <= 64) or (size >= 512 and size <= 2048)))
{
abi = size;
pref = size;
force_pref = true;
} else if (self.target.cpu.arch == .s390x and size == 128) {
abi = 64;
pref = 64;
force_pref = false;
} else if (self.target.cpu.arch == .ve and (size >= 64 and size <= 16384)) {
abi = 64;
pref = 64;
force_abi = true;
force_pref = true;
},
.float => switch (self.target.cpu.arch) {
.amdgcn => if (size == 128) {
abi = size;
pref = size;
},
.arc => if (size == 32 or size == 64) {
abi = 32;
pref = 32;
force_abi = true;
force_pref = size == 32;
},
.avr, .msp430, .sparc64 => if (size != 32 and size != 64) return,
.csky => if (size == 32 or size == 64) {
abi = 32;
pref = 32;
force_abi = true;
force_pref = true;
},
.hexagon => if (size == 32 or size == 64) {
force_abi = true;
},
.ve, .xtensa => if (size == 64) {
abi = size;
pref = size;
},
.wasm32, .wasm64 => if (self.target.os.tag == .emscripten and size == 128) {
abi = 64;
pref = 64;
},
else => {},
},
.aggregate => if (self.target.os.tag == .uefi or self.target.os.tag == .windows or
self.target.cpu.arch.isArm())
{
pref = @min(pref, self.target.ptrBitWidth());
} else switch (self.target.cpu.arch) {
.arc, .csky => {
abi = 0;
pref = 32;
},
.hexagon => {
abi = 0;
pref = 0;
},
.m68k => {
abi = 0;
pref = 16;
},
.msp430 => {
abi = 8;
pref = 8;
},
.s390x => {
abi = 8;
pref = 16;
},
else => {},
},
}
if (kind != .vector and self.target.cpu.arch == .avr) {
force_abi = true;
abi = 8;
pref = 8;
}
if (!force_abi and abi == default_abi and pref == default_pref) return;
try writer.print("-{c}", .{@tagName(kind)[0]});
if (size != 0) try writer.print("{d}", .{size});
try writer.print(":{d}", .{abi});
if (pref != abi or force_pref) try writer.print(":{d}", .{pref});
}
};
pub const Object = struct {
gpa: Allocator,
builder: Builder,
pt: Zcu.PerThread,
debug_compile_unit: Builder.Metadata,
debug_enums_fwd_ref: Builder.Metadata,
debug_globals_fwd_ref: Builder.Metadata,
debug_enums: std.ArrayListUnmanaged(Builder.Metadata),
debug_globals: std.ArrayListUnmanaged(Builder.Metadata),
debug_file_map: std.AutoHashMapUnmanaged(Zcu.File.Index, Builder.Metadata),
debug_type_map: std.AutoHashMapUnmanaged(Type, Builder.Metadata),
debug_unresolved_namespace_scopes: std.AutoArrayHashMapUnmanaged(InternPool.NamespaceIndex, Builder.Metadata),
target: std.Target,
/// Ideally we would use `llvm_module.getNamedFunction` to go from *Decl to LLVM function,
/// but that has some downsides:
/// * we have to compute the fully qualified name every time we want to do the lookup
/// * for externally linked functions, the name is not fully qualified, but when
/// a Decl goes from exported to not exported and vice-versa, we would use the wrong
/// version of the name and incorrectly get function not found in the llvm module.
/// * it works for functions not all globals.
/// Therefore, this table keeps track of the mapping.
nav_map: std.AutoHashMapUnmanaged(InternPool.Nav.Index, Builder.Global.Index),
/// Same deal as `decl_map` but for anonymous declarations, which are always global constants.
uav_map: std.AutoHashMapUnmanaged(InternPool.Index, Builder.Global.Index),
/// Maps enum types to their corresponding LLVM functions for implementing the `tag_name` instruction.
enum_tag_name_map: std.AutoHashMapUnmanaged(InternPool.Index, Builder.Global.Index),
/// Serves the same purpose as `enum_tag_name_map` but for the `is_named_enum_value` instruction.
named_enum_map: std.AutoHashMapUnmanaged(InternPool.Index, Builder.Function.Index),
/// Maps Zig types to LLVM types. The table memory is backed by the GPA of
/// the compiler.
/// TODO when InternPool garbage collection is implemented, this map needs
/// to be garbage collected as well.
type_map: TypeMap,
/// The LLVM global table which holds the names corresponding to Zig errors.
/// Note that the values are not added until `emit`, when all errors in
/// the compilation are known.
error_name_table: Builder.Variable.Index,
/// Memoizes a null `?usize` value.
null_opt_usize: Builder.Constant,
/// When an LLVM struct type is created, an entry is inserted into this
/// table for every zig source field of the struct that has a corresponding
/// LLVM struct field. comptime fields are not included. Zero-bit fields are
/// mapped to a field at the correct byte, which may be a padding field, or
/// are not mapped, in which case they are semantically at the end of the
/// struct.
/// The value is the LLVM struct field index.
/// This is denormalized data.
struct_field_map: std.AutoHashMapUnmanaged(ZigStructField, c_uint),
/// Values for `@llvm.used`.
used: std.ArrayListUnmanaged(Builder.Constant),
const ZigStructField = struct {
struct_ty: InternPool.Index,
field_index: u32,
};
pub const Ptr = if (dev.env.supports(.llvm_backend)) *Object else noreturn;
pub const TypeMap = std.AutoHashMapUnmanaged(InternPool.Index, Builder.Type);
pub fn create(arena: Allocator, comp: *Compilation) !Ptr {
dev.check(.llvm_backend);
const gpa = comp.gpa;
const target = comp.root_mod.resolved_target.result;
const llvm_target_triple = try targetTriple(arena, target);
var builder = try Builder.init(.{
.allocator = gpa,
.strip = comp.config.debug_format == .strip,
.name = comp.root_name,
.target = target,
.triple = llvm_target_triple,
});
errdefer builder.deinit();
builder.data_layout = try builder.fmt("{}", .{DataLayoutBuilder{ .target = target }});
const debug_compile_unit, const debug_enums_fwd_ref, const debug_globals_fwd_ref =
if (!builder.strip)
debug_info: {
// We fully resolve all paths at this point to avoid lack of
// source line info in stack traces or lack of debugging
// information which, if relative paths were used, would be
// very location dependent.
// TODO: the only concern I have with this is WASI as either host or target, should
// we leave the paths as relative then?
// TODO: This is totally wrong. In dwarf, paths are encoded as relative to
// a particular directory, and then the directory path is specified elsewhere.
// In the compiler frontend we have it stored correctly in this
// way already, but here we throw all that sweet information
// into the garbage can by converting into absolute paths. What
// a terrible tragedy.
const compile_unit_dir = blk: {
if (comp.zcu) |zcu| m: {
const d = try zcu.main_mod.root.joinString(arena, "");
if (d.len == 0) break :m;
if (std.fs.path.isAbsolute(d)) break :blk d;
break :blk std.fs.realpathAlloc(arena, d) catch break :blk d;
}
break :blk try std.process.getCwdAlloc(arena);
};
const debug_file = try builder.debugFile(
try builder.metadataString(comp.root_name),
try builder.metadataString(compile_unit_dir),
);
const debug_enums_fwd_ref = try builder.debugForwardReference();
const debug_globals_fwd_ref = try builder.debugForwardReference();
const debug_compile_unit = try builder.debugCompileUnit(
debug_file,
// Don't use the version string here; LLVM misparses it when it
// includes the git revision.
try builder.metadataStringFmt("zig {d}.{d}.{d}", .{
build_options.semver.major,
build_options.semver.minor,
build_options.semver.patch,
}),