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add spi nand driver #50690

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2 changes: 2 additions & 0 deletions drivers/flash/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,8 @@
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_TELINK_B91 soc_flash_b91.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_XMC4XXX soc_flash_xmc4xxx.c)
zephyr_library_sources_ifdef(CONFIG_SPI_FLASH_AT45 spi_flash_at45.c)
zephyr_library_sources_ifdef(CONFIG_SPI_NAND_SOFTWARE_ECC bch.c)
zephyr_library_sources_ifdef(CONFIG_SPI_NAND spi_nand.c)
zephyr_library_sources_ifdef(CONFIG_SPI_NOR spi_nor.c)
# zephyr-keep-sorted-stop

Expand All @@ -84,7 +86,7 @@
dt_chosen(chosen_flash PROPERTY "zephyr,flash")
dt_prop(compat_flash PATH ${chosen_flash} PROPERTY compatible)
if(compat_flash MATCHES "nxp,imx-flexspi-nor")
zephyr_code_relocate(FILES flash_mcux_flexspi_nor.c LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)

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drivers/flash/CMakeLists.txt:89 sorted block has out-of-order line at 87
zephyr_code_relocate(FILES jesd216.c LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)
elseif(compat_flash MATCHES "nxp,imx-flexspi-mx25um51345g")
zephyr_code_relocate(FILES flash_mcux_flexspi_mx25um51345g.c LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)
Expand All @@ -98,18 +100,18 @@
if(CONFIG_SOC_SERIES_STM32H7X)
zephyr_library_sources_ifdef(CONFIG_DT_HAS_ST_STM32H7_FLASH_CONTROLLER_ENABLED flash_stm32h7x.c)
elseif(CONFIG_SOC_SERIES_STM32H7RSX)
zephyr_library_sources_ifdef(CONFIG_DT_HAS_ST_STM32H7_FLASH_CONTROLLER_ENABLED flash_stm32h7x.c)

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drivers/flash/CMakeLists.txt:103 CMakeStyle
elseif(CONFIG_SOC_SERIES_STM32WBAX)

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drivers/flash/CMakeLists.txt:104 CMakeStyle
if(CONFIG_BT_STM32WBA)
# BLE is enabled. Use implementation over Flash Manager for coexistence with RF activities

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drivers/flash/CMakeLists.txt:106 CMakeStyle
zephyr_library_sources(flash_stm32wba_fm.c)
else()
zephyr_library_sources_ifdef(CONFIG_DT_HAS_ST_STM32_FLASH_CONTROLLER_ENABLED flash_stm32.c flash_stm32wbax.c)
endif()
elseif(CONFIG_SOC_SERIES_STM32WB0X)
zephyr_library_sources_ifdef(CONFIG_DT_HAS_ST_STM32WB0_FLASH_CONTROLLER_ENABLED flash_stm32wb0x.c)
else()

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drivers/flash/CMakeLists.txt:113 CMakeStyle
if(CONFIG_DT_HAS_ST_STM32_FLASH_CONTROLLER_ENABLED)

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drivers/flash/CMakeLists.txt:114 CMakeStyle
zephyr_library_sources(flash_stm32.c)

# zephyr-keep-sorted-start
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1 change: 1 addition & 0 deletions drivers/flash/Kconfig
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Expand Up @@ -181,6 +181,7 @@ source "drivers/flash/Kconfig.lpc"
source "drivers/flash/Kconfig.max32"
source "drivers/flash/Kconfig.mcux"
source "drivers/flash/Kconfig.mspi"
source "drivers/flash/Kconfig.nand"
source "drivers/flash/Kconfig.nor"
source "drivers/flash/Kconfig.nordic_qspi_nor"
source "drivers/flash/Kconfig.npcx_fiu"
Expand Down
48 changes: 48 additions & 0 deletions drivers/flash/Kconfig.nand
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Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
# Copyright (c) 2022-2025 Macronix International Co., Ltd.
# SPDX-License-Identifier: Apache-2.0

menuconfig SPI_NAND
bool "SPI NAND Flash"
default y
depends on DT_HAS_JEDEC_SPI_NAND_ENABLED
select FLASH_HAS_DRIVER_ENABLED
select FLASH_HAS_EXPLICIT_ERASE
select FLASH_HAS_PAGE_LAYOUT
select SPI

if SPI_NAND

config SPI_NAND_INIT_PRIORITY
int "SPI NAND init priority"
default 80
help
Device driver initialization priority.
Device is connected to SPI bus, it has to
be initialized after SPI driver.

config SPI_NAND_SOFTWARE_ECC
bool "Software ECC for SPI NAND flash"
help
Enable this option to use software-based ECC (Error Correction Code)
when accessing SPI NAND flash devices. This is useful for platforms
that do not support hardware ECC, or when additional software control
over ECC handling is required.

config SPI_NAND_ECC_STEP_SIZE
int "ECC step size (bytes)"
default 512
depends on SPI_NAND_SOFTWARE_ECC
help
Specifies the ECC (Error Correction Code) step size in bytes for SPI NAND
flash operations. This value determines how many bytes of data are protected
by one ECC block.

config SPI_NAND_BCH_HEAP_SIZE
int "BCH heap size (bytes)"
default 51200
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@de-nordic de-nordic Nov 25, 2025

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How is user supposed to know how to calculate this so that flash driver would not error out on lack of mem?

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@daniel-0723 daniel-0723 Nov 29, 2025 •
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image image image image image

@de-nordic In this case, the ECC chunk size (CONFIG_SPI_NAND_ECC_STEP_SIZE) is 512 bytes (4096 bits), which means the parameter m must be at least 13 to fully cover the chunk (with m = 12, the last bit would not be protected). The Flash ECC capability is 8 bits (t = 8). In addition to the LUT heap, an extra 3 KB is required to satisfy other BCH heap requirements. Therefore, the total memory size is approximately 32 KB + 3 KB = 35 KB, which we have verified in testing.

depends on SPI_NAND_SOFTWARE_ECC
help
Specify the heap size (in bytes) reserved for BCH (Bose-Chaudhuri-Hocquenghem)
error correction in SPI NAND flash operations.

endif # SPI_NAND
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