What is SPI_HALF_DUPLEX in Zephyr

[RichardSWheatley]

Zephyr says:

    /**
    * @name SPI duplex mode
    * @{
    *
    * Some controllers support half duplex transfer, which results in 3-wire usage.
    * By default, full duplex will prevail.
    */
    #define SPI_FULL_DUPLEX		(0U << 11)
    #define SPI_HALF_DUPLEX		(1U << 11)
    /** @} */

[ThreeEights]

Well, in the SPI world, "3-wire" means there are 3 wires between the host and the peripheral: CS, CLK, and a single DATA line, instead of the more common 4 wires with separate DATA_OUT and DATA_IN lines. A 4-wire configuration could run in either full-duplex or half-duplex, but from what I've seen, most Zephyr SPI drivers don't support half-duplex operation. A 3-wire configuration, of course, can only run in half-duplex; in my case, trying to talk to a 3-wire device with a Raspberry Pi Pico, I have flip the direction of the GPIO line between sending a command and receiving the data (and making sure the flip it back before sending the next command!).

[RichardSWheatley]

I agree but it doesn't say 3-wire configuration. It says "3-wire usage".

I think they need to fix the wording.

But you didn't answer the poll.

[tobiwan88]

THe original definition of spi is only full duplex 4 wire (good old motorola spi) https://onlinedocs.microchip.com/pr/GUID-835917AF-E521-4046-AD59-DCB458EB8466-en-US-1/index.html?GUID-E4682943-46B9-4A20-A62C-33E8FD3343A3

From the missuses implementations i saw they always define 3 wire as a half duplex, E.g. https://www.st.com/en/microcontrollers-microprocessors/stm32l0-series/documentation.html