drivers: mspi: mspi_dw: Add support for nrf-mspi peripheral

The nrf-mspi peripheral is similar to EXMIF on nrf54h20
but supports DMA and slave-mode. The wrapper around
the SSI IP is also different with DMA features.

Signed-off-by: David Jewsbury [email protected]

Author: Hi-Im-David

drivers/mspi/mspi_dw_vendor_specific.h

@@ -13,22 +13,22 @@
 
 #include <nrf.h>
 
-static inline void vendor_specific_init(const struct device *dev)
+static inline void vendor_specific_init(const struct device *dev, const struct mspi_dw_config * config)
 {
 	ARG_UNUSED(dev);
 
 	NRF_EXMIF->EVENTS_CORE = 0;
 	NRF_EXMIF->INTENSET = BIT(EXMIF_INTENSET_CORE_Pos);
 }
 
-static inline void vendor_specific_suspend(const struct device *dev)
+static inline void vendor_specific_suspend(const struct device *dev, const struct mspi_dw_config * config)
 {
 	ARG_UNUSED(dev);
 
 	NRF_EXMIF->TASKS_STOP = 1;
 }
 
-static inline void vendor_specific_resume(const struct device *dev)
+static inline void vendor_specific_resume(const struct device *dev, const struct mspi_dw_config * config)
 {
 	ARG_UNUSED(dev);
 
@@ -46,15 +46,15 @@ static inline void vendor_specific_resume(const struct device *dev)
 	} while (rxftlr != rxftlr_mod);
 }
 
-static inline void vendor_specific_irq_clear(const struct device *dev)
+static inline void vendor_specific_irq_clear(const struct device *dev, const struct mspi_dw_config * config)
 {
 	ARG_UNUSED(dev);
 
 	NRF_EXMIF->EVENTS_CORE = 0;
 }
 
 #if defined(CONFIG_MSPI_XIP)
-static inline int vendor_specific_xip_enable(const struct device *dev,
+static inline int vendor_specific_xip_enable(const struct device *dev, const struct mspi_dw_config * config,
 					     const struct mspi_dev_id *dev_id,
 					     const struct mspi_xip_cfg *cfg)
 {
@@ -77,7 +77,7 @@ static inline int vendor_specific_xip_enable(const struct device *dev,
 	return 0;
 }
 
-static inline int vendor_specific_xip_disable(const struct device *dev,
+static inline int vendor_specific_xip_disable(const struct device *dev, const struct mspi_dw_config * config,
 					      const struct mspi_dev_id *dev_id,
 					      const struct mspi_xip_cfg *cfg)
 {
@@ -97,3 +97,193 @@ static inline int vendor_specific_xip_disable(const struct device *dev,
 #endif /* defined(CONFIG_MSPI_XIP) */
 
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_exmif) */
+
+#define MSPI_DT_DRV_COMPAT nordic_nrf_mspi
+#if DT_HAS_COMPAT_STATUS_OKAY(MSPI_DT_DRV_COMPAT)
+
+#include <nrf.h>
+
+static inline void vendor_specific_init(const struct device *dev, const struct mspi_dw_config * config)
+{
+	NRF_QSPI_Type *preg = (NRF_QSPI_Type *)config->wrapper_regs;
+	
+	preg->EVENTS_CORE = 0;
+	preg->EVENTS_DMA.DONE = 0;
+
+	preg->INTENSET |= BIT(QSPI_INTENSET_CORE_Pos);
+	preg->INTENSET |= BIT(QSPI_INTENSET_DMADONE_Pos);
+
+}
+
+static inline void vendor_specific_suspend(const struct device *dev, const struct mspi_dw_config * config)
+{
+	NRF_QSPI_Type *preg = (NRF_QSPI_Type *)config->wrapper_regs;
+	ARG_UNUSED(dev);
+
+	preg->ENABLE = 0; 
+}
+
+static inline void vendor_specific_resume(const struct device *dev, const struct mspi_dw_config * config)
+{
+	NRF_QSPI_Type *preg = (NRF_QSPI_Type *)config->wrapper_regs;
+	ARG_UNUSED(dev);
+
+	preg->ENABLE = 1;
+
+	/* Try to write an SSI register and wait until the write is successful
+	 * to ensure that the clock that drives the SSI core is ready.
+	 */
+	uint32_t rxftlr = read_rxftlr(dev);
+	uint32_t rxftlr_mod = rxftlr ^ 1;
+
+	do {
+		write_rxftlr(dev, rxftlr_mod);
+		rxftlr = read_rxftlr(dev);
+	} while (rxftlr != rxftlr_mod);
+}
+
+static inline void vendor_specific_irq_clear(const struct device *dev, const struct mspi_dw_config * config)
+{
+	ARG_UNUSED(dev);
+	NRF_QSPI_Type *preg = (NRF_QSPI_Type *)config->wrapper_regs;
+	preg->EVENTS_CORE = 0;
+	preg->EVENTS_DMA.DONE = 0;
+}
+
+/* DMA support */
+
+#define EVDMA_ATTR_LEN_Pos (0UL)
+#define EVDMA_ATTR_LEN_Msk (0x00FFFFFFUL)
+
+#define EVDMA_ATTR_ATTR_Pos (24UL)
+#define EVDMA_ATTR_ATTR_Msk (0x3FUL << EVDMA_ATTR_ATTR_Pos)
+
+#define EVDMA_ATTR_32AXI_Pos (30UL)
+#define EVDMA_ATTR_32AXI_Msk (0x1UL << EVDMA_ATTR_32AXI_Pos)
+
+#define EVDMA_ATTR_EVENTS_Pos (31UL)
+#define EVDMA_ATTR_EVENTS_Msk (0x1UL << EVDMA_ATTR_EVENTS_Pos)
+
+typedef enum {
+  EVDMA_BYTE_SWAP = 0,
+  EVDMA_JOBLIST = 1,
+  EVDMA_BUFFER_FILL = 2,
+  EVDMA_FIXED_ATTR = 3,
+  EVDMA_STATIC_ADDR = 4,
+  EVDMA_PLAIN_DATA_BUF_WR = 5,
+
+  EVDMA_PLAIN_DATA = 0x3f
+} EVDMA_ATTR_Type;
+
+typedef struct {
+  uint8_t* addr;
+  uint32_t attr;
+} EVDMA_JOB_Type;
+
+#define EVDMA_JOB(BUFFER, SIZE, ATTR) \
+  (EVDMA_JOB_Type) { .addr = (uint8_t*)BUFFER, .attr = (ATTR << EVDMA_ATTR_ATTR_Pos | SIZE) }
+#define EVDMA_NULL_JOB() \
+  (EVDMA_JOB_Type) { .addr = (uint8_t*)0, .attr = 0 }
+typedef struct {
+    EVDMA_JOB_Type* tx_job;
+    EVDMA_JOB_Type* rx_job;
+} QSPI_TRANSFER_LIST_Type;
+
+/* Number of jobs needed for transmit trasaction */
+#define NUM_JOBS 5
+/* Just support 1 trasaction for each peripheral as concurrent transactions aren't supported yet*/
+#define MAX_CONCURR_TRANSACTIONS 1
+#define NUM_LISTS DT_NUM_INST_STATUS_OKAY(MSPI_DT_DRV_COMPAT)
+#define DMA_TRANSFER_LIST_SIZE (sizeof(QSPI_TRANSFER_LIST_Type) + sizeof(EVDMA_JOB_Type) * \
+                                NUM_JOBS * MAX_CONCURR_TRANSACTIONS)
+#define DMA_TRANSFER_LIST_ALIGN 4
+K_MEM_SLAB_DEFINE(dma_transfer_list_slab, DMA_TRANSFER_LIST_SIZE, NUM_LISTS, DMA_TRANSFER_LIST_ALIGN);
+
+static inline void vendor_specific_enable_dma_irq(const struct device *dev, const struct mspi_dw_config * config)
+{
+	ARG_UNUSED(dev);
+	NRF_QSPI_Type *preg = (NRF_QSPI_Type *)config->wrapper_regs;
+	preg->INTENSET = BIT(QSPI_INTENSET_DMADONE_Pos);
+}
+
+static inline void vendor_specific_start_dma_xfer(const struct device *dev, const struct mspi_dw_config * config)
+{
+	ARG_UNUSED(dev);
+	NRF_QSPI_Type *preg = (NRF_QSPI_Type *)config->wrapper_regs;
+	preg->TASKS_START = 1;
+}
+
+/* Temporarily hard coded as not in MDK yet */
+#define QSPI_TMOD_OFFSET (0x490UL)
+#define QSPI_TMOD_RX_ONLY (0x2)
+static inline int vendor_specific_setup_dma_xfer(const struct device *dev, const struct mspi_dw_config * config,
+	                                        const struct mspi_xfer_packet *packet, const struct mspi_xfer *xfer, struct mspi_dw_data * dev_data)
+{
+	ARG_UNUSED(dev);
+	NRF_QSPI_Type *preg = (NRF_QSPI_Type *)config->wrapper_regs;
+
+	void *transfer_list_ptr;
+	int rc = k_mem_slab_alloc(&dma_transfer_list_slab, &transfer_list_ptr, K_NO_WAIT);
+	if (rc < 0) {
+		return rc;
+	}
+
+	/* Create DMA transfer list based on whether it is an RX or TX transfer */
+	QSPI_TRANSFER_LIST_Type *transfer_list = (QSPI_TRANSFER_LIST_Type *)transfer_list_ptr;
+	dev_data->dma_transfer_list = (void*) transfer_list;
+	/* Right after transfer_list */
+	EVDMA_JOB_Type *joblist = (EVDMA_JOB_Type *)(transfer_list + 1); 
+
+        if(packet->dir == MSPI_TX) {
+			preg->CONFIG.RXTRANSFERLENGTH = 0;
+			joblist[0] = EVDMA_JOB(&packet->cmd, xfer->cmd_length, EVDMA_PLAIN_DATA);
+			joblist[1] = EVDMA_JOB(&packet->address, xfer->addr_length, EVDMA_PLAIN_DATA);
+			joblist[2] = EVDMA_JOB(packet->data_buf, packet->num_bytes, EVDMA_PLAIN_DATA);
+			joblist[3] = EVDMA_NULL_JOB();
+			joblist[4] = EVDMA_NULL_JOB();
+			transfer_list->tx_job = &joblist[0];
+			transfer_list->rx_job = &joblist[3];
+		}
+        else {
+			preg->CONFIG.RXTRANSFERLENGTH = ((packet->num_bytes + xfer->addr_length + xfer->cmd_length) >> dev_data->bytes_per_frame_exp) -1;
+			joblist[0] = EVDMA_JOB(packet->data_buf, packet->num_bytes, EVDMA_PLAIN_DATA);
+			joblist[1] = EVDMA_NULL_JOB();
+			transfer_list->tx_job = &joblist[1];
+			transfer_list->rx_job = &joblist[0];
+			/*
+			* In slave mode, a tmod register in the wrapper also needs to be set. Currently
+			* the address not in MDK so temp fix.
+			*/
+			uintptr_t addr = (uintptr_t)preg + QSPI_TMOD_OFFSET;
+
+			sys_write32(QSPI_TMOD_RX_ONLY, addr);
+        }
+
+	preg->CONFIG.TXBURSTLENGTH = (config->tx_fifo_depth_minus_1+1)-config->dma_tx_data_level;
+	preg->CONFIG.RXBURSTLENGTH = config->dma_rx_data_level+1;
+	preg->DMA.CONFIG.LISTPTR = (uint32_t)transfer_list;
+	preg->INTEN = BIT(QSPI_INTEN_DMADONE_Pos);
+
+        return 0;
+}
+
+static inline void vendor_specific_free_dma_transfer_list(const struct device *dev, struct mspi_dw_data * dev_data) {
+        ARG_UNUSED(dev);
+        k_mem_slab_free(&dma_transfer_list_slab, dev_data->dma_transfer_list);
+}
+
+static inline bool vendor_specific_dma_accessible_check(const struct device *dev, 
+							const struct mspi_dw_config * config, uint8_t *data_buf ) {
+	ARG_UNUSED(dev);
+	NRF_QSPI_Type *preg = (NRF_QSPI_Type *)config->wrapper_regs;
+	return nrf_dma_accessible_check(preg, data_buf);
+}
+
+static inline bool vendor_specific_read_dma_irq(const struct device *dev, 
+							const struct mspi_dw_config * config ) {
+	ARG_UNUSED(dev);
+	NRF_QSPI_Type *preg = (NRF_QSPI_Type *)config->wrapper_regs;
+	return (bool) preg->EVENTS_DMA.DONE;
+}
+
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(MSPI_DT_DRV_COMPAT) */

dts/bindings/mspi/nordic,nrf-mspi.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic MSPI Interface using SSI IP
+
+compatible: "nordic,nrf-mspi"
+
+include: snps,designware-ssi.yaml