boards: shields: add st_b_dsi_mb1314 shield (DSI display)

Addition of a new shield which embeds a round DSI display
gvo,g1120tb101 of 390x390 pixels, with a touchpanel.
This shield enables it via usage of the LTDC and DSI
of the STM32.

Touchpanel isn't yet supported in this commit and will
be added later on in an additional commit.

Signed-off-by: Alain Volmat <[email protected]>

Author: Alain Volmat

boards/shields/st_b_dsi_mb1314/Kconfig.shield

@@ -0,0 +1,6 @@
+# Copyright (c) 2025 STMicroelectronics
+
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_ST_B_DSI_MB1314
+	def_bool $(shields_list_contains,st_b_dsi_mb1314)

boards/shields/st_b_dsi_mb1314/boards/stm32l4r9i_disco.conf

@@ -0,0 +1,5 @@
+CONFIG_DISPLAY=y
+CONFIG_MIPI_DSI=y
+CONFIG_STM32_LTDC_RGB565=y
+CONFIG_STM32_LTDC_FB_NUM=1
+CONFIG_GPIO_HOGS_INIT_PRIORITY=71

boards/shields/st_b_dsi_mb1314/boards/stm32l4r9i_disco.overlay

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
+
+/ {
+	chosen {
+		zephyr,display = &ltdc;
+		/* SRAM0 is too small to hold a framebuffer */
+		zephyr,sram = &sram2;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(16)>; /* 16MHz */
+	status = "okay";
+};
+
+&ltdc {
+	status = "okay";
+
+	width = <390>;
+	height = <390>;
+	pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
+
+	display-timings {
+		compatible = "zephyr,panel-timing";
+		de-active = <0>;
+		pixelclk-active = <0>;
+		hsync-active = <0>;
+		vsync-active = <0>;
+		hsync-len = <1>;
+		vsync-len = <1>;
+		hback-porch = <1>;
+		vback-porch = <1>;
+		hfront-porch = <1>;
+		vfront-porch = <1>;
+	};
+	def-back-color-red = <0x0>;
+	def-back-color-green = <0x0>;
+	def-back-color-blue = <0x0>;
+};
+
+&mfx {
+	dsi_3v3_pwron {
+		gpio-hog;
+		gpios = <8 GPIO_ACTIVE_LOW>;
+		output-high;
+		line-name = "DSI_3V3_PWRON";
+	};
+
+	dsi_1v8_pwron {
+		gpio-hog;
+		gpios = <18 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "DSI_1v8_PWRON";
+	};
+};
+
+&pllsai2 {
+	/* PLLSAI2 is here to generate the PCLK to feed the DSI
+	 * We need to feed roughly 500Mbps. PCLK depends on format
+	 * For 24bit (RGB888) format, we need roughly 20.8 MHz.  (Actually target 15 MHz)
+	 *   div-m = 1, mul-n = 60, div-r = 4, div-divr = 4
+	 *
+	 * PCLK = MSI (4MHz) * mul-n / (div-m * div-r * div-divr)
+	 */
+	status = "okay";
+	div-m = <1>;
+	mul-n = <60>;
+	div-r = <4>;
+	div-divr = <4>;
+	clocks = <&clk_msi>;
+};
+
+&zephyr_mipi_dsi {
+	status = "okay";
+
+	/* DSI HOST dedicated PLL to generate 62.5 MHz from 16MHz
+	 * source clock, in order to generate 500Mbps on single lane
+	 *
+	 * F_VCO = CLK_IN / pll-idf * 2 * pll-ndiv
+	 * PHI = F_VCO / 2 / (1 << pll-odf) = lane_byte_clk
+	 *     = 25 MHz / 5 * 2 * 100 / 2 / (1<<0) / 8 = 62.5 MHz
+	 */
+	pll-ndiv = <125>;
+	pll-idf = <4>;
+	pll-odf = <0>;
+
+	phy-timings = <33 /* ClockLaneHS2LPTime */
+		       30 /* ClockLaneLP2HSTime */
+		       11 /* DataLaneHS2LPTime */
+		       21 /* DataLaneLP2HSTime */
+		       0 /* DataLaneMaxReadTime */
+		       7 /* StopWaitTime */>;
+
+	host-timeouts = <1 /* TimeoutCkdiv */
+			 0 /* HighSpeedTransmissionTimeout */
+			 0 /* LowPowerReceptionTimeout */
+			 0 /* HighSpeedReadTimeout */
+			 0 /* LowPowerReadTimeout */
+			 0 /* HighSpeedWriteTimeout */
+			 0 /* HighSpeedWritePrespMode */
+			 0 /* LowPowerWriteTimeout */
+			 0 /* BTATimeout */>;
+
+	vs-active-high;
+	hs-active-high;
+	de-active-high;
+
+	lp-rx-filter=<10000>;
+
+	g1120tb101: panel@0 {
+		compatible = "gvo,g1120tb101";
+		reg = <0x0>;
+		height = <390>;
+		width = <390>;
+		data-lanes = <1>;
+		reset-gpios = <&mfx 10 GPIO_ACTIVE_LOW>;
+
+		pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
+	};
+};