Skip to content

Commit 44bfd32

Browse files
Daniel Wagenknechtgalak
Daniel Wagenknecht
authored and
galak
committed
dts: spi: add remaining SPI fixup defines for STM32
Add SPI fixup defines on STM32 SoC family level for all SPIs that are supported on one or more SOCs of that SoC family. Signed-off-by: Daniel Wagenknecht <[email protected]>
1 parent ab20e83 commit 44bfd32

File tree

5 files changed

+63
-13
lines changed

5 files changed

+63
-13
lines changed

‎arch/arm/soc/st_stm32/stm32f0/dts.fixup‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,11 @@
3131
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
3232
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0
3333

34+
#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
35+
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
36+
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
37+
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0
38+
3439
#define FLASH_DEV_BASE_ADDRESS ST_STM32F0_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0
3540
#define FLASH_DEV_NAME ST_STM32F0_FLASH_CONTROLLER_40022000_LABEL
3641

‎arch/arm/soc/st_stm32/stm32f1/dts.fixup‎

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -28,9 +28,19 @@
2828
#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V1_40005800_IRQ_ERROR
2929
#define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
3030

31-
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS
32-
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY
33-
#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL
34-
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0
31+
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS
32+
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY
33+
#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL
34+
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0
35+
36+
#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_40003800_BASE_ADDRESS
37+
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_40003800_IRQ_0_PRIORITY
38+
#define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL
39+
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0
40+
41+
#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_40003C00_BASE_ADDRESS
42+
#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
43+
#define CONFIG_SPI_3_NAME ST_STM32_SPI_40003C00_LABEL
44+
#define CONFIG_SPI_3_IRQ ST_STM32_SPI_40003C00_IRQ_0
3545

3646
/* End of SoC Level DTS fixup file */

‎arch/arm/soc/st_stm32/stm32f3/dts.fixup‎

Lines changed: 19 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -30,15 +30,25 @@
3030
#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_IRQ_ERROR
3131
#define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
3232

33-
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
34-
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
35-
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
36-
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0
37-
38-
#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
39-
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
40-
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
41-
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0
33+
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
34+
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
35+
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
36+
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0
37+
38+
#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
39+
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
40+
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
41+
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0
42+
43+
#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
44+
#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
45+
#define CONFIG_SPI_3_NAME ST_STM32_SPI_FIFO_40003C00_LABEL
46+
#define CONFIG_SPI_3_IRQ ST_STM32_SPI_FIFO_40003C00_IRQ_0
47+
48+
#define CONFIG_SPI_4_BASE_ADDRESS ST_STM32_SPI_FIFO_40013C00_BASE_ADDRESS
49+
#define CONFIG_SPI_4_IRQ_PRI ST_STM32_SPI_FIFO_40013C00_IRQ_0_PRIORITY
50+
#define CONFIG_SPI_4_NAME ST_STM32_SPI_FIFO_40013C00_LABEL
51+
#define CONFIG_SPI_4_IRQ ST_STM32_SPI_FIFO_40013C00_IRQ_0
4252

4353
#define FLASH_DEV_BASE_ADDRESS ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0
4454
#define FLASH_DEV_NAME ST_STM32F3_FLASH_CONTROLLER_40022000_LABEL

‎arch/arm/soc/st_stm32/stm32f4/dts.fixup‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,26 @@
6060
#define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL
6161
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0
6262

63+
#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_40003C00_BASE_ADDRESS
64+
#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
65+
#define CONFIG_SPI_3_NAME ST_STM32_SPI_40003C00_LABEL
66+
#define CONFIG_SPI_3_IRQ ST_STM32_SPI_40003C00_IRQ_0
67+
68+
#define CONFIG_SPI_4_BASE_ADDRESS ST_STM32_SPI_40013400_BASE_ADDRESS
69+
#define CONFIG_SPI_4_IRQ_PRI ST_STM32_SPI_40013400_IRQ_0_PRIORITY
70+
#define CONFIG_SPI_4_NAME ST_STM32_SPI_40013400_LABEL
71+
#define CONFIG_SPI_4_IRQ ST_STM32_SPI_40013400_IRQ_0
72+
73+
#define CONFIG_SPI_5_BASE_ADDRESS ST_STM32_SPI_40015000_BASE_ADDRESS
74+
#define CONFIG_SPI_5_IRQ_PRI ST_STM32_SPI_40015000_IRQ_0_PRIORITY
75+
#define CONFIG_SPI_5_NAME ST_STM32_SPI_40015000_LABEL
76+
#define CONFIG_SPI_5_IRQ ST_STM32_SPI_40015000_IRQ_0
77+
78+
#define CONFIG_SPI_6_BASE_ADDRESS ST_STM32_SPI_40015400_BASE_ADDRESS
79+
#define CONFIG_SPI_6_IRQ_PRI ST_STM32_SPI_40015400_IRQ_0_PRIORITY
80+
#define CONFIG_SPI_6_NAME ST_STM32_SPI_40015400_LABEL
81+
#define CONFIG_SPI_6_IRQ ST_STM32_SPI_40015400_IRQ_0
82+
6383
#define FLASH_DEV_BASE_ADDRESS ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS_0
6484
#define FLASH_DEV_NAME ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL
6585

‎arch/arm/soc/st_stm32/stm32l4/dts.fixup‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,11 @@
5353
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
5454
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0
5555

56+
#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
57+
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
58+
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
59+
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0
60+
5661
#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
5762
#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
5863
#define CONFIG_SPI_3_NAME ST_STM32_SPI_FIFO_40003C00_LABEL

0 commit comments

Comments
 (0)