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Daniel Wagenknechtgalak
Daniel Wagenknecht
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dts: stm32: add SPI nodes to dtsi files
Add SPI nodes to existing dtsi files. Signed-off-by: Daniel Wagenknecht <[email protected]>
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‎dts/arm/st/stm32f072.dtsi‎

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*/
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#include <st/stm32f0.dtsi>
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/ {
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soc {
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <26 3>;
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status = "disabled";
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label = "SPI_2";
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};
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};
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};

‎dts/arm/st/stm32f091.dtsi‎

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*/
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#include <st/stm32f0.dtsi>
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/ {
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soc {
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <26 3>;
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status = "disabled";
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label = "SPI_2";
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};
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};
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};

‎dts/arm/st/stm32f103Xb.dtsi‎

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*/
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#include <st/stm32f1.dtsi>
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/ {
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soc {
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/* spi2 is present on all STM32F103xB SoCs except
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* STM32F103TB. Delete node in stm32f103tb.dtsi.
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*/
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spi2: spi@40003800 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <36 5>;
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status = "disabled";
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label = "SPI_2";
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};
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};
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};

‎dts/arm/st/stm32f103Xe.dtsi‎

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*/
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#include <st/stm32f103Xb.dtsi>
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/ {
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soc {
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spi3: spi@40003C00 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003C00 0x400>;
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interrupts = <51 5>;
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status = "disabled";
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};
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};
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};

‎dts/arm/st/stm32f373.dtsi‎

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status = "disabled";
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label= "I2C_2";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <36 5>;
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status = "disabled";
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label = "SPI_2";
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};
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spi3: spi@40003C00 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003C00 0x400>;
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interrupts = <51 5>;
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status = "disabled";
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label = "SPI_3";
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};
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};
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};

‎dts/arm/st/stm32f401.dtsi‎

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*/
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#include <st/stm32f4.dtsi>
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/ {
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soc {
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spi2: spi@40003800 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <36 5>;
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status = "disabled";
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label = "SPI_2";
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};
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spi3: spi@40003C00 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003C00 0x400>;
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interrupts = <51 5>;
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status = "disabled";
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label = "SPI_3";
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};
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};
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};

‎dts/arm/st/stm32f411.dtsi‎

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*/
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#include <st/stm32f401.dtsi>
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/ {
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soc {
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spi4: spi@40013400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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interrupts = <84 5>;
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status = "disabled";
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label = "SPI_4";
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};
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spi5: spi@40015000 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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interrupts = <85 5>;
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status = "disabled";
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label = "SPI_5";
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};
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};
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};

‎dts/arm/st/stm32f429.dtsi‎

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status = "disabled";
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label = "UART_8";
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};
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spi4: spi@40013400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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interrupts = <84 5>;
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status = "disabled";
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label = "SPI_4";
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};
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};
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};

‎dts/arm/st/stm32f469.dtsi‎

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status = "disabled";
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label = "UART_8";
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};
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spi4: spi@40013400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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interrupts = <84 5>;
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status = "disabled";
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label = "SPI_4";
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};
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/* spi5 is present on all STM32F469XX SoCs except
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* STM32F469vX and STM32F469zX SoCs. Delete node in
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* stm32f469vX.dtsi and stm32f469zX.dtsi.
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*/
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spi5: spi@40015000 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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interrupts = <85 5>;
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status = "disabled";
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label = "SPI_5";
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};
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/* spi6 is present on all STM32F469XX SoCs except
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* STM32F469vX and STM32F469zX SoCs. Delete node in
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* stm32f469vX.dtsi and stm32f469zX.dtsi.
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*/
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spi6: spi@40015400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015400 0x400>;
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interrupts = <86 5>;
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status = "disabled";
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label = "SPI_6";
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};
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};
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};

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