drivers: dma: siwx91x: Bug fix for regular DMA transfers

smalae · kartben · commit 19e4c56e231b · 2025-04-22T16:54:11.000+02:00
Addressed an issue where regular/non-scatter-gather DMA
transfers were not explicitly using the primary DMA descriptor
structure. This ensures a smooth regular DMA transfer after
any scatter gather transfer.

Signed-off-by: Sai Santhosh Malae &lt;Santhosh.Malae@silabs.com&gt;
diff --git a/drivers/dma/dma_silabs_siwx91x.c b/drivers/dma/dma_silabs_siwx91x.c
@@ -343,6 +343,9 @@ static int siwx91x_direct_chan_config(const struct device *dev, RSI_UDMA_HANDLE_
 		channel_control.dstInc = UDMA_DST_INC_NONE;
 	}
 
+	/* Clear the CHNL_PRI_ALT_CLR to use primary DMA descriptor structure */
+	sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->CHNL_PRI_ALT_CLR);
+
 	status = UDMAx_ChannelConfigure(&udma_resources, (uint8_t)channel,
 					config->head_block->source_address,
 					config->head_block->dest_address,

Original file line number	Diff line number	Diff line change
`@@ -343,6 +343,9 @@ static int siwx91x_direct_chan_config(const struct device *dev, RSI_UDMA_HANDLE_`
`343`	`343`	`channel_control.dstInc = UDMA_DST_INC_NONE;`
`344`	`344`	`}`
`345`	`345`
	`346`	`+ /* Clear the CHNL_PRI_ALT_CLR to use primary DMA descriptor structure */`
	`347`	`+ sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->CHNL_PRI_ALT_CLR);`
	`348`	`+`
`346`	`349`	`status = UDMAx_ChannelConfigure(&udma_resources, (uint8_t)channel,`
`347`	`350`	`config->head_block->source_address,`
`348`	`351`	`config->head_block->dest_address,`