tests: riscv: Implement unit tests for PMP memattr configuration and state

fsammoura1980 · fsammoura1980 · commit 00006f0fe012 · 2025-11-05T06:10:58.000Z
This commit implements a new unit test suite to validate the
integration of Device Tree memory attributes (`zephyr,memory-attr`)
with the RISC-V Physical Memory Protection (PMP) hardware.

The test suite includes:
1. **`test_pmp_devicetree_memattr_config`**: Verifies that the PMP
   Control and Status Registers (CSRs) are programmed correctly based
   on the memory regions defined with `zephyr,memory-attr` in the
   Device Tree. It iterates through the active PMP entries and
   asserts a match against the expected DT-defined regions.
2. **`test_riscv_mprv_mpp_config`**: Checks the initial state of the
   Machine Privilege Register Virtualization (MPRV) bit and Machine
   Previous Privilege (MPP) field in the `mstatus` CSR to ensure PMP
   is configured for correct privilege level switching during boot.
3. **`test_dt_pmp_perm_conversion`**: Validates the
   `DT_MEM_RISCV_TO_PMP_PERM` macro to ensure the conversion from
   Device Tree memory attribute flags to RISC-V PMP permission bits
   (R/W/X) is correct.

Signed-off-by: Firas Sammoura &lt;fsammoura@google.com&gt;
diff --git a/arch/riscv/core/pmp.c b/arch/riscv/core/pmp.c
@@ -68,11 +68,9 @@ LOG_MODULE_REGISTER(mpu);
  * @param start Pointer to where the calculated start address should be stored.
  * @param end Pointer to where the calculated end address should be stored.
  */
-static void pmp_decode_region(uint8_t cfg_byte,
-                              unsigned long *pmp_addr,
-                              unsigned int index,
-                              unsigned long *start,
-                              unsigned long *end)
+IF_DISABLED(CONFIG_ZTEST, (static))
+void pmp_decode_region(uint8_t cfg_byte, unsigned long *pmp_addr, unsigned int index,
+		       unsigned long *start, unsigned long *end)
 {
 	unsigned long tmp;
 	unsigned long pmp_addr_val = pmp_addr[index];
@@ -139,7 +137,8 @@ static void print_pmp_entries(unsigned int pmp_start, unsigned int pmp_end,
  * @param pmp_cfg Pointer to the array where the CSR contents will be stored.
  * @param pmp_cfg_size The size of the pmp_cfg array, measured in unsigned long entries.
  */
-static inline void z_riscv_pmp_read_config(unsigned long *pmp_cfg, size_t pmp_cfg_size)
+IF_DISABLED(CONFIG_ZTEST, (static inline))
+void z_riscv_pmp_read_config(unsigned long *pmp_cfg, size_t pmp_cfg_size)
 {
 	__ASSERT(pmp_cfg_size == (size_t)(CONFIG_PMP_SLOTS / PMPCFG_STRIDE),
 		 "Invalid PMP config array size");
@@ -205,7 +204,8 @@ static inline void z_riscv_pmp_write_config(unsigned long *pmp_cfg, size_t pmp_c
  * @param pmp_addr Pointer to the array where the CSR contents will be stored.
  * @param pmp_addr_size The size of the pmp_addr array, measured in unsigned long entries.
  */
-static inline void z_riscv_pmp_read_addr(unsigned long *pmp_addr, size_t pmp_addr_size)
+IF_DISABLED(CONFIG_ZTEST, (static inline))
+void z_riscv_pmp_read_addr(unsigned long *pmp_addr, size_t pmp_addr_size)
 {
 	__ASSERT(pmp_addr_size == (size_t)(CONFIG_PMP_SLOTS), "PMP address array size mismatch");
 
diff --git a/arch/riscv/include/pmp.h b/arch/riscv/include/pmp.h
@@ -24,4 +24,11 @@ void z_riscv_pmp_usermode_init(struct k_thread *thread);
 void z_riscv_pmp_usermode_prepare(struct k_thread *thread);
 void z_riscv_pmp_usermode_enable(struct k_thread *thread);
 
+#ifdef CONFIG_ZTEST
+void z_riscv_pmp_read_config(unsigned long *pmp_cfg, size_t pmp_cfg_size);
+void z_riscv_pmp_read_addr(unsigned long *pmp_addr, size_t pmp_addr_size);
+void pmp_decode_region(uint8_t cfg_byte, unsigned long *pmp_addr, unsigned int index,
+		       unsigned long *start, unsigned long *end);
+#endif /* CONFIG_ZTEST */
+
 #endif /* PMP_H_ */
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/CMakeLists.txt b/tests/arch/riscv/pmp/mem-attr-entries/CMakeLists.txt
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(riscv_pmp)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
+
+target_include_directories(app PRIVATE
+  ${ZEPHYR_BASE}/kernel/include
+  ${ZEPHYR_BASE}/arch/${ARCH}/include
+  )
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/memattr_mapping.overlay b/tests/arch/riscv/pmp/mem-attr-entries/memattr_mapping.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 Google LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-riscv.h>
+
+/ {
+	memattr_region1: memattr_region1@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 0x20000>;
+		zephyr,memory-region = "MEMATTR_REGION1";
+		zephyr,memory-attr = <(DT_MEM_RISCV_TYPE_IO_R |
+				      DT_MEM_RISCV_TYPE_IO_W |
+				      DT_MEM_RISCV_TYPE_IO_X)>;
+	};
+
+	memattr_region2: memattr_region2@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80020000 0x30000>;
+		zephyr,memory-region = "MEMATTR_REGION2";
+		zephyr,memory-attr = <(DT_MEM_RISCV_TYPE_IO_R |
+				      DT_MEM_RISCV_TYPE_IO_W |
+				      DT_MEM_RISCV_TYPE_IO_X)>;
+	};
+};
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/prj.conf b/tests/arch/riscv/pmp/mem-attr-entries/prj.conf
@@ -0,0 +1,2 @@
+CONFIG_ZTEST=y
+CONFIG_MEM_ATTR=y
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/src/main.c b/tests/arch/riscv/pmp/mem-attr-entries/src/main.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2025 Google LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel_internal.h>
+#include <zephyr/mem_mgmt/mem_attr.h>
+#include <zephyr/tc_util.h>
+#include <zephyr/ztest.h>
+
+/* Checks if the Machine Privilege Register Virtualization (MPRV) bit in mstatus is 1 (enabled). */
+static bool riscv_mprv_is_enabled(void)
+{
+	return csr_read(mstatus) & MSTATUS_MPRV;
+}
+
+/* Checks if the Machine Previous Privilege (MPP) field in mstatus is set to M-Mode (0b11). */
+static bool riscv_mpp_is_m_mode(void)
+{
+	return (csr_read(mstatus) & MSTATUS_MPP) == MSTATUS_MPP;
+}
+
+/* Helper structure to define the expected PMP regions derived from the Device Tree. */
+struct expected_region {
+	uintptr_t base;
+	size_t size;
+	uint8_t perm;
+	bool found;
+};
+
+/*
+ * Extract base address, size, and permission for the memory regions
+ * defined in the Device Tree under the 'memattr' nodes.
+ */
+static struct expected_region dt_regions[] = {
+	{.base = DT_REG_ADDR(DT_NODELABEL(memattr_region1)),
+	 .size = DT_REG_SIZE(DT_NODELABEL(memattr_region1)),
+	 .perm = DT_MEM_RISCV_TO_PMP_PERM(
+		 DT_PROP(DT_NODELABEL(memattr_region1), zephyr_memory_attr)),
+	 .found = false},
+	{.base = DT_REG_ADDR(DT_NODELABEL(memattr_region2)),
+	 .size = DT_REG_SIZE(DT_NODELABEL(memattr_region2)),
+	 .perm = DT_MEM_RISCV_TO_PMP_PERM(
+		 DT_PROP(DT_NODELABEL(memattr_region2), zephyr_memory_attr)),
+	 .found = false}};
+
+ZTEST(riscv_pmp_memattr_entries, test_pmp_devicetree_memattr_config)
+{
+	const size_t num_pmpcfg_regs = CONFIG_PMP_SLOTS / sizeof(unsigned long);
+	const size_t num_pmpaddr_regs = CONFIG_PMP_SLOTS;
+
+	unsigned long current_pmpcfg_regs[num_pmpcfg_regs];
+	unsigned long current_pmpaddr_regs[num_pmpaddr_regs];
+
+	/* Read the current PMP configuration from the control registers */
+	z_riscv_pmp_read_config(current_pmpcfg_regs, num_pmpcfg_regs);
+	z_riscv_pmp_read_addr(current_pmpaddr_regs, num_pmpaddr_regs);
+
+	const uint8_t *const current_pmp_cfg_entries = (const uint8_t *)current_pmpcfg_regs;
+
+	for (unsigned int index = 0; index < CONFIG_PMP_SLOTS; ++index) {
+		unsigned long start, end;
+		uint8_t cfg_byte = current_pmp_cfg_entries[index];
+
+		/* Decode the configured PMP region (start and end addresses) */
+		pmp_decode_region(cfg_byte, current_pmpaddr_regs, index, &start, &end);
+
+		/* Compare the decoded region against the list of expected DT regions */
+		for (size_t i = 0; i < ARRAY_SIZE(dt_regions); ++i) {
+			if ((start == dt_regions[i].base) &&
+			    (end == dt_regions[i].base + dt_regions[i].size - 1) &&
+			    ((cfg_byte & 0x07) == dt_regions[i].perm)) {
+
+				dt_regions[i].found = true;
+				break;
+			}
+		}
+	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(dt_regions); i++) {
+		zassert_true(dt_regions[i].found,
+			     "PMP entry for DT region %zu (base 0x%lx, size 0x%zx, perm 0x%x) not "
+			     "found.",
+			     i + 1, dt_regions[i].base, dt_regions[i].size, dt_regions[i].perm);
+	}
+}
+
+ZTEST(riscv_pmp_memattr_entries, test_riscv_mprv_mpp_config)
+{
+	zassert_true(riscv_mprv_is_enabled(),
+		     "MPRV should be enabled (1) to use the privilege specified by the MPP field.");
+
+	zassert_false(riscv_mpp_is_m_mode(),
+		      "MPP should be set to 0x00 (U-Mode) before execution.");
+}
+
+ZTEST(riscv_pmp_memattr_entries, test_dt_pmp_perm_conversion)
+{
+	uint8_t result;
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(0);
+	zassert_equal(result, 0, "Expected 0, got 0x%x", result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_EMPTY);
+	zassert_equal(result, 0, "Expected 0, got 0x%x", result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_R);
+	zassert_equal(result, PMP_R, "Expected PMP_R (0x%x), got 0x%x", PMP_R, result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_W);
+	zassert_equal(result, PMP_W, "Expected PMP_W (0x%x), got 0x%x", PMP_W, result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_X);
+	zassert_equal(result, PMP_X, "Expected PMP_X (0x%x), got 0x%x", PMP_X, result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_R | DT_MEM_RISCV_TYPE_IO_W);
+	zassert_equal(result, PMP_R | PMP_W, "Expected R|W (0x%x), got 0x%x", PMP_R | PMP_W,
+		      result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_R | DT_MEM_RISCV_TYPE_IO_W |
+					  DT_MEM_RISCV_TYPE_IO_X);
+	zassert_equal(result, PMP_R | PMP_W | PMP_X, "Expected R|W|X (0x%x), got 0x%x",
+		      PMP_R | PMP_W | PMP_X, result);
+}
+
+ZTEST_SUITE(riscv_pmp_memattr_entries, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/testcase.yaml b/tests/arch/riscv/pmp/mem-attr-entries/testcase.yaml
@@ -0,0 +1,11 @@
+common:
+  platform_allow:
+    - qemu_riscv32
+    - qemu_riscv32e
+    - qemu_riscv64
+  filter: CONFIG_RISCV_PMP
+
+tests:
+  arch.riscv.pmp.memattr.entries:
+    extra_args:
+      DTC_OVERLAY_FILE="memattr_mapping.overlay"

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	`+CONFIG_ZTEST=y`
	`2`	`+CONFIG_MEM_ATTR=y`